Re: Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
On Thu, Sep 4, 2014 at 12:02 PM, Chao Xie wrote:
>
>
> At 2014-09-04 01:55:37, "Mike Turquette" wrote:
>>Quoting Chao Xie (2014-08-25 21:38:18)
>>> From: Chao Xie
>>>
>>> Some SOCes have this kind of the gate clock
>>> 1. There are some bits to control the gate not only one bit.
>>> 2. Some clocks has operations of "out of reset" and "enable".
>>>To enable clock, we need do "out of reset" and "enable".
>>>To disable clock, we may not need "set to reset". It depends
>>>on the SOCes' design.
>>
>>Are there any other IP blocks affected by the "out of reset" and "set to
>>reset" states? I wonder if you might benefit from the reset controller
>>framework? For example see,
>>
>>drivers/clk/qcom/gcc-apq8084.c
>>
>>
>
>>
> Thanks to point it out.
> To use the reset framework, there are some problem.
> 1. the reset bit is combined with the clocks disable/enable bits in same
> register. Seperating setting them means spinlock
> protection and 2 operations for read-update the bits.
>
>
> except that, i think reset framework can bring some benefits.
Check out the sunxi gates clk
(drivers/clk/sunxi/clk-sunxi.c:sunxi_gates_clk_setup())
In particular, the usb gate clk, which has gates and reset controls
in the same register. The driver registers separate clk gates and reset
controls for each bit, but uses the same spinlock for all bits.
ChenYu
> Even without the reset bit, we still need the gate clocks.
> The enable/disable is not a bit operation, and it is bits operation for some
> devices.
> In fact i want to use it to replace the old clk-apbc and clk-apmu clocks.
>
>>> +static int mmp_clk_gate_enable(struct clk_hw *hw)
>>> +{
>>> + struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
>>> + struct clk *clk = hw->clk;
>>> + unsigned long flags = 0;
>>> + unsigned long rate;
>>> + u32 tmp;
>>> +
>>> + if (gate->lock)
>>> + spin_lock_irqsave(gate->lock, flags);
>>> +
>>> + tmp = readl(gate->reg);
>>> + tmp &= ~gate->mask;
>>> + tmp |= gate->val_enable;
>>> + writel(tmp, gate->reg);
>>> +
>>> + if (gate->lock)
>>> + spin_unlock_irqrestore(gate->lock, flags);
>>> +
>>> + if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
>>> + rate = __clk_get_rate(clk);
>>> + /* Need delay 2 cycles. */
>>> + udelay(200/rate);
>>
>>How long are these delays? Long enough to warrant using clk_prepare
>>instead of clk_enable? Are these clocks enabled from interrupt context?
>
>>
> For power optimization, some clocks need to be enabled/disable in interrupt
> context.
> The worst delay is rate=32KHZ, so the delay is 62.5us.
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Re:Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
At 2014-09-04 01:55:37, "Mike Turquette" wrote:
>Quoting Chao Xie (2014-08-25 21:38:18)
>> From: Chao Xie
>>
>> Some SOCes have this kind of the gate clock
>> 1. There are some bits to control the gate not only one bit.
>> 2. Some clocks has operations of "out of reset" and "enable".
>>To enable clock, we need do "out of reset" and "enable".
>>To disable clock, we may not need "set to reset". It depends
>>on the SOCes' design.
>
>Are there any other IP blocks affected by the "out of reset" and "set to
>reset" states? I wonder if you might benefit from the reset controller
>framework? For example see,
>
>drivers/clk/qcom/gcc-apq8084.c
>
>
>
Thanks to point it out.
To use the reset framework, there are some problem.
1. the reset bit is combined with the clocks disable/enable bits in same
register. Seperating setting them means spinlock
protection and 2 operations for read-update the bits.
except that, i think reset framework can bring some benefits.
Even without the reset bit, we still need the gate clocks.
The enable/disable is not a bit operation, and it is bits operation for some
devices.
In fact i want to use it to replace the old clk-apbc and clk-apmu clocks.
>> +static int mmp_clk_gate_enable(struct clk_hw *hw)
>> +{
>> + struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
>> + struct clk *clk = hw->clk;
>> + unsigned long flags = 0;
>> + unsigned long rate;
>> + u32 tmp;
>> +
>> + if (gate->lock)
>> + spin_lock_irqsave(gate->lock, flags);
>> +
>> + tmp = readl(gate->reg);
>> + tmp &= ~gate->mask;
>> + tmp |= gate->val_enable;
>> + writel(tmp, gate->reg);
>> +
>> + if (gate->lock)
>> + spin_unlock_irqrestore(gate->lock, flags);
>> +
>> + if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
>> + rate = __clk_get_rate(clk);
>> + /* Need delay 2 cycles. */
>> + udelay(200/rate);
>
>How long are these delays? Long enough to warrant using clk_prepare
>instead of clk_enable? Are these clocks enabled from interrupt context?
>
For power optimization, some clocks need to be enabled/disable in interrupt
context.
The worst delay is rate=32KHZ, so the delay is 62.5us.
>Regards,
>Mike
N嫥叉靣笡y氊b瞂千v豝�)藓{.n�+壏{睉赙zXФ洝塄}财爖�:+v墾�珣赙zZ+€�+zf＂穐殘啳嗃iz� 畐ア�?櫒璀�&�)撷f旟^j谦y呩@A玜囤
0鹅h�鍜i
Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
Quoting Chao Xie (2014-08-25 21:38:18)
> From: Chao Xie
>
> Some SOCes have this kind of the gate clock
> 1. There are some bits to control the gate not only one bit.
> 2. Some clocks has operations of "out of reset" and "enable".
>To enable clock, we need do "out of reset" and "enable".
>To disable clock, we may not need "set to reset". It depends
>on the SOCes' design.
Are there any other IP blocks affected by the "out of reset" and "set to
reset" states? I wonder if you might benefit from the reset controller
framework? For example see,
drivers/clk/qcom/gcc-apq8084.c
> +static int mmp_clk_gate_enable(struct clk_hw *hw)
> +{
> + struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
> + struct clk *clk = hw->clk;
> + unsigned long flags = 0;
> + unsigned long rate;
> + u32 tmp;
> +
> + if (gate->lock)
> + spin_lock_irqsave(gate->lock, flags);
> +
> + tmp = readl(gate->reg);
> + tmp &= ~gate->mask;
> + tmp |= gate->val_enable;
> + writel(tmp, gate->reg);
> +
> + if (gate->lock)
> + spin_unlock_irqrestore(gate->lock, flags);
> +
> + if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
> + rate = __clk_get_rate(clk);
> + /* Need delay 2 cycles. */
> + udelay(200/rate);
How long are these delays? Long enough to warrant using clk_prepare
instead of clk_enable? Are these clocks enabled from interrupt context?
Regards,
Mike
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Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
Quoting Chao Xie (2014-08-25 21:38:18)
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set to reset. It depends
on the SOCes' design.
Are there any other IP blocks affected by the out of reset and set to
reset states? I wonder if you might benefit from the reset controller
framework? For example see,
drivers/clk/qcom/gcc-apq8084.c
snip
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw-clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_enable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ if (gate-flags MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
How long are these delays? Long enough to warrant using clk_prepare
instead of clk_enable? Are these clocks enabled from interrupt context?
Regards,
Mike
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Re:Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
At 2014-09-04 01:55:37, Mike Turquette mturque...@linaro.org wrote:
Quoting Chao Xie (2014-08-25 21:38:18)
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set to reset. It depends
on the SOCes' design.
Are there any other IP blocks affected by the out of reset and set to
reset states? I wonder if you might benefit from the reset controller
framework? For example see,
drivers/clk/qcom/gcc-apq8084.c
snip
Thanks to point it out.
To use the reset framework, there are some problem.
1. the reset bit is combined with the clocks disable/enable bits in same
register. Seperating setting them means spinlock
protection and 2 operations for read-update the bits.
except that, i think reset framework can bring some benefits.
Even without the reset bit, we still need the gate clocks.
The enable/disable is not a bit operation, and it is bits operation for some
devices.
In fact i want to use it to replace the old clk-apbc and clk-apmu clocks.
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw-clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_enable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ if (gate-flags MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
How long are these delays? Long enough to warrant using clk_prepare
instead of clk_enable? Are these clocks enabled from interrupt context?
For power optimization, some clocks need to be enabled/disable in interrupt
context.
The worst delay is rate=32KHZ, so the delay is 62.5us.
Regards,
Mike
N嫥叉靣笡y氊b瞂千v豝�)藓{.n�+壏{睉赙zXФ洝塄}财爖�j:+v墾�珣赙zZ+€�+zf＂穐殘啳嗃iz� 畐ア�?櫒璀��)撷f旟^j谦y呩@A玜囤
0鹅h�鍜i
Re: Re: [PATCH 06/12] clk: mmp: add mmp private gate clock
On Thu, Sep 4, 2014 at 12:02 PM, Chao Xie xiechao_m...@163.com wrote:
At 2014-09-04 01:55:37, Mike Turquette mturque...@linaro.org wrote:
Quoting Chao Xie (2014-08-25 21:38:18)
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set to reset. It depends
on the SOCes' design.
Are there any other IP blocks affected by the out of reset and set to
reset states? I wonder if you might benefit from the reset controller
framework? For example see,
drivers/clk/qcom/gcc-apq8084.c
snip
Thanks to point it out.
To use the reset framework, there are some problem.
1. the reset bit is combined with the clocks disable/enable bits in same
register. Seperating setting them means spinlock
protection and 2 operations for read-update the bits.
except that, i think reset framework can bring some benefits.
Check out the sunxi gates clk
(drivers/clk/sunxi/clk-sunxi.c:sunxi_gates_clk_setup())
In particular, the usb gate clk, which has gates and reset controls
in the same register. The driver registers separate clk gates and reset
controls for each bit, but uses the same spinlock for all bits.
ChenYu
Even without the reset bit, we still need the gate clocks.
The enable/disable is not a bit operation, and it is bits operation for some
devices.
In fact i want to use it to replace the old clk-apbc and clk-apmu clocks.
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw-clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_enable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ if (gate-flags MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
How long are these delays? Long enough to warrant using clk_prepare
instead of clk_enable? Are these clocks enabled from interrupt context?
For power optimization, some clocks need to be enabled/disable in interrupt
context.
The worst delay is rate=32KHZ, so the delay is 62.5us.
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 06/12] clk: mmp: add mmp private gate clock
From: Chao Xie
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of "out of reset" and "enable".
To enable clock, we need do "out of reset" and "enable".
To disable clock, we may not need "set to reset". It depends
on the SOCes' design.
3. It is not always that "1" is to enable while "0" is to disable
when write register.
So we have to define the "mask", "enable_val", "disable_val" for
this kind of gate clock.
Signed-off-by: Chao Xie
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-gate.c | 133 +
drivers/clk/mmp/clk.h | 21 +++
3 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-gate.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 8bfee860..2855f7b 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -2,7 +2,7 @@
# Makefile for mmp specific clk
#
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644
index 000..adbd9d6
--- /dev/null
+++ b/drivers/clk/mmp/clk-gate.c
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw->clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+ tmp &= ~gate->mask;
+ tmp |= gate->val_enable;
+ writel(tmp, gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
+ }
+
+ return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+ tmp &= ~gate->mask;
+ tmp |= gate->val_disable;
+ writel(tmp, gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ return (tmp & gate->mask) == gate->val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+ .enable = mmp_clk_gate_enable,
+ .disable = mmp_clk_gate_disable,
+ .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+ unsigned int gate_flags, spinlock_t *lock)
+{
+ struct mmp_clk_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ pr_err("%s:%s could not allocate gate clk\n", __func__, name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = _clk_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? _name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_gate assignments */
+ gate->reg = reg;
+ gate->mask = mask;
+ gate->val_enable = val_enable;
+ gate->val_disable = val_disable;
+ gate->flags = gate_flags;
+ gate->lock = lock;
+ gate->hw.init =
+
+ clk = clk_register(dev, >hw);
+
+ if (IS_ERR(clk))
+ kfree(gate);
+
+ return clk;
+}
diff --git
[PATCH 06/12] clk: mmp: add mmp private gate clock
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set to reset. It depends
on the SOCes' design.
3. It is not always that 1 is to enable while 0 is to disable
when write register.
So we have to define the mask, enable_val, disable_val for
this kind of gate clock.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-gate.c | 133 +
drivers/clk/mmp/clk.h | 21 +++
3 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-gate.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 8bfee860..2855f7b 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -2,7 +2,7 @@
# Makefile for mmp specific clk
#
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644
index 000..adbd9d6
--- /dev/null
+++ b/drivers/clk/mmp/clk-gate.c
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie chao@marvell.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/err.h
+#include linux/delay.h
+
+#include clk.h
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw-clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_enable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ if (gate-flags MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
+ }
+
+ return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_disable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ return (tmp gate-mask) == gate-val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+ .enable = mmp_clk_gate_enable,
+ .disable = mmp_clk_gate_disable,
+ .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+ unsigned int gate_flags, spinlock_t *lock)
+{
+ struct mmp_clk_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ pr_err(%s:%s could not allocate gate clk\n, __func__, name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = mmp_clk_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_gate assignments */
+ gate-reg = reg;
+ gate-mask = mask;
+ gate-val_enable = val_enable;
+ gate-val_disable = val_disable;
+ gate-flags = gate_flags;
+ gate-lock = lock;
+ gate-hw.init = init;
+
+ clk = clk_register(dev, gate-hw);
+
+ if
[PATCH 06/12] clk: mmp: add mmp private gate clock
From: Chao Xie
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of "out of reset" and "enable".
To enable clock, we need do "out of reset" and "enable".
To disable clock, we may not need "set to reset". It depends
on the SOCes' design.
3. It is not always that "1" is to enable while "0" is to disable
when write register.
So we have to define the "mask", "enable_val", "disable_val" for
this kind of gate clock.
Signed-off-by: Chao Xie
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-gate.c | 133 +
drivers/clk/mmp/clk.h | 21 +++
3 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-gate.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 8bfee860..2855f7b 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -2,7 +2,7 @@
# Makefile for mmp specific clk
#
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644
index 000..adbd9d6
--- /dev/null
+++ b/drivers/clk/mmp/clk-gate.c
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw->clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+ tmp &= ~gate->mask;
+ tmp |= gate->val_enable;
+ writel(tmp, gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
+ }
+
+ return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+ tmp &= ~gate->mask;
+ tmp |= gate->val_disable;
+ writel(tmp, gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate->lock)
+ spin_lock_irqsave(gate->lock, flags);
+
+ tmp = readl(gate->reg);
+
+ if (gate->lock)
+ spin_unlock_irqrestore(gate->lock, flags);
+
+ return (tmp & gate->mask) == gate->val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+ .enable = mmp_clk_gate_enable,
+ .disable = mmp_clk_gate_disable,
+ .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+ unsigned int gate_flags, spinlock_t *lock)
+{
+ struct mmp_clk_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ pr_err("%s:%s could not allocate gate clk\n", __func__, name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = _clk_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? _name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_gate assignments */
+ gate->reg = reg;
+ gate->mask = mask;
+ gate->val_enable = val_enable;
+ gate->val_disable = val_disable;
+ gate->flags = gate_flags;
+ gate->lock = lock;
+ gate->hw.init =
+
+ clk = clk_register(dev, >hw);
+
+ if (IS_ERR(clk))
+ kfree(gate);
+
+ return clk;
+}
diff --git
[PATCH 06/12] clk: mmp: add mmp private gate clock
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set to reset. It depends
on the SOCes' design.
3. It is not always that 1 is to enable while 0 is to disable
when write register.
So we have to define the mask, enable_val, disable_val for
this kind of gate clock.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-gate.c | 133 +
drivers/clk/mmp/clk.h | 21 +++
3 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-gate.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index 8bfee860..2855f7b 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -2,7 +2,7 @@
# Makefile for mmp specific clk
#
-obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o
+obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
new file mode 100644
index 000..adbd9d6
--- /dev/null
+++ b/drivers/clk/mmp/clk-gate.c
@@ -0,0 +1,133 @@
+/*
+ * mmp gate clock operation source file
+ *
+ * Copyright (C) 2014 Marvell
+ * Chao Xie chao@marvell.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk-provider.h
+#include linux/slab.h
+#include linux/io.h
+#include linux/err.h
+#include linux/delay.h
+
+#include clk.h
+
+/*
+ * Some clocks will have mutiple bits to enable the clocks, and
+ * the bits to disable the clock is not same as enabling bits.
+ */
+
+#define to_clk_mmp_gate(hw)container_of(hw, struct mmp_clk_gate, hw)
+
+static int mmp_clk_gate_enable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ struct clk *clk = hw-clk;
+ unsigned long flags = 0;
+ unsigned long rate;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_enable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ if (gate-flags MMP_CLK_GATE_NEED_DELAY) {
+ rate = __clk_get_rate(clk);
+ /* Need delay 2 cycles. */
+ udelay(200/rate);
+ }
+
+ return 0;
+}
+
+static void mmp_clk_gate_disable(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+ tmp = ~gate-mask;
+ tmp |= gate-val_disable;
+ writel(tmp, gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+}
+
+static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
+ unsigned long flags = 0;
+ u32 tmp;
+
+ if (gate-lock)
+ spin_lock_irqsave(gate-lock, flags);
+
+ tmp = readl(gate-reg);
+
+ if (gate-lock)
+ spin_unlock_irqrestore(gate-lock, flags);
+
+ return (tmp gate-mask) == gate-val_enable;
+}
+
+const struct clk_ops mmp_clk_gate_ops = {
+ .enable = mmp_clk_gate_enable,
+ .disable = mmp_clk_gate_disable,
+ .is_enabled = mmp_clk_gate_is_enabled,
+};
+
+struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
+ unsigned int gate_flags, spinlock_t *lock)
+{
+ struct mmp_clk_gate *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ pr_err(%s:%s could not allocate gate clk\n, __func__, name);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = mmp_clk_gate_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_gate assignments */
+ gate-reg = reg;
+ gate-mask = mask;
+ gate-val_enable = val_enable;
+ gate-val_disable = val_disable;
+ gate-flags = gate_flags;
+ gate-lock = lock;
+ gate-hw.init = init;
+
+ clk = clk_register(dev, gate-hw);
+
+ if
