Re: [PATCH 1/1] dt-bindings: MIPS: Document Ingenic SoCs binding.
On Tue, May 26, 2020 at 09:10:29PM +0200, Paul Cercueil wrote: > Hi Zhou, > > Le mer. 27 mai 2020 à 1:07, 周琰杰 (Zhou Yanjie) > a écrit : > > Document the available properties for the SoC root node and the > > CPU nodes of the devicetree for the Ingenic XBurst SoCs. > > > > Tested-by: H. Nikolaus Schaller > > Tested-by: Paul Boddie > > Signed-off-by: 周琰杰 (Zhou Yanjie) > > --- > > .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 > > ++ > > 1 file changed, 57 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > > b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > > new file mode 100644 > > index ..afb02071a756 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml > > @@ -0,0 +1,57 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Bindings for Ingenic XBurst family CPUs > > + > > +maintainers: > > + - 周琰杰 (Zhou Yanjie) > > + > > +description: > > + Ingenic XBurst family CPUs shall have the following properties. > > + > > +properties: > > + compatible: > > +oneOf: > > + > > + - description: Ingenic XBurst®1 CPU Cores > > +items: > > Strip the 'items', put the enum directly. > > > + enum: > > +- ingenic,xburst-mxu1.0 > > +- ingenic,xburst-fpu1.0-mxu1.1 > > +- ingenic,xburst-fpu2.0-mxu2.0 > > + > > + - description: Ingenic XBurst®2 CPU Cores > > +items: > > Same here. > > > + enum: > > +- ingenic,xburst2-fpu2.1-mxu2.1-smt > > + > > + reg: > > +maxItems: 1 > > + > > +required: > > + - device_type > > + - compatible > > + - reg > > device_type is not in the list of your properties. It doesn't have to be. There's already a schema for it in dt-schema. It's not always required there, so requiring here is fine. It's an oddity of json-schema, but what's listed in required doesn't have to be in 'properties'. Rob
Re: [PATCH 1/1] dt-bindings: MIPS: Document Ingenic SoCs binding.
Hi Paul, 在 2020/5/27 上午3:10, Paul Cercueil 写道: Hi Zhou, Le mer. 27 mai 2020 à 1:07, 周琰杰 (Zhou Yanjie) a écrit : Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index ..afb02071a756 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) + +description: + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: + oneOf: + + - description: Ingenic XBurst®1 CPU Cores + items: Strip the 'items', put the enum directly. Sure, I'll drop it in the next version. + enum: + - ingenic,xburst-mxu1.0 + - ingenic,xburst-fpu1.0-mxu1.1 + - ingenic,xburst-fpu2.0-mxu2.0 + + - description: Ingenic XBurst®2 CPU Cores + items: Same here. Sure. + enum: + - ingenic,xburst2-fpu2.1-mxu2.1-smt + + reg: + maxItems: 1 + +required: + - device_type + - compatible + - reg device_type is not in the list of your properties. Also, I think you need a clock in there. Sure, I will add it. Thanks and best regards! -Paul + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; + }; + }; +... -- 2.11.0
Re: [PATCH 1/1] dt-bindings: MIPS: Document Ingenic SoCs binding.
Hi Zhou, Le mer. 27 mai 2020 à 1:07, 周琰杰 (Zhou Yanjie) a écrit : Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index ..afb02071a756 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) + +description: + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: +oneOf: + + - description: Ingenic XBurst®1 CPU Cores +items: Strip the 'items', put the enum directly. + enum: +- ingenic,xburst-mxu1.0 +- ingenic,xburst-fpu1.0-mxu1.1 +- ingenic,xburst-fpu2.0-mxu2.0 + + - description: Ingenic XBurst®2 CPU Cores +items: Same here. + enum: +- ingenic,xburst2-fpu2.1-mxu2.1-smt + + reg: +maxItems: 1 + +required: + - device_type + - compatible + - reg device_type is not in the list of your properties. Also, I think you need a clock in there. -Paul + +examples: + - | +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; + }; +}; +... -- 2.11.0
[PATCH 1/1] dt-bindings: MIPS: Document Ingenic SoCs binding.
Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index ..afb02071a756 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) + +description: + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: +oneOf: + + - description: Ingenic XBurst®1 CPU Cores +items: + enum: +- ingenic,xburst-mxu1.0 +- ingenic,xburst-fpu1.0-mxu1.1 +- ingenic,xburst-fpu2.0-mxu2.0 + + - description: Ingenic XBurst®2 CPU Cores +items: + enum: +- ingenic,xburst2-fpu2.1-mxu2.1-smt + + reg: +maxItems: 1 + +required: + - device_type + - compatible + - reg + +examples: + - | +cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; + }; +}; +... -- 2.11.0