Re: [PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-07-05 Thread Paul Walmsley 
On Wed, 25 Jun 2014, Kishon Vijay Abraham I wrote:

> Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
> Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
> for pcie1 phy and pcie2 phy.
> 
> Cc: Tony Lindgren 
> Cc: Russell King 
> Cc: Paul Walmsley 
> Signed-off-by: Kishon Vijay Abraham I 
> Tested-by: Kishon Vijay Abraham I 

Thanks, queued for v3.17 with Rajendra's ack.


- Paul
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Re: [PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-07-05 Thread Paul Walmsley 
On Wed, 25 Jun 2014, Kishon Vijay Abraham I wrote:

 Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
 Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
 for pcie1 phy and pcie2 phy.
 
 Cc: Tony Lindgren t...@atomide.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Paul Walmsley p...@pwsan.com
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 Tested-by: Kishon Vijay Abraham I kis...@ti.com

Thanks, queued for v3.17 with Rajendra's ack.


- Paul
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-07-03 Thread Rajendra Nayak 
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
> Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
> for pcie1 phy and pcie2 phy.
> 
> Cc: Tony Lindgren 
> Cc: Russell King 
> Cc: Paul Walmsley 
> Signed-off-by: Kishon Vijay Abraham I 
> Tested-by: Kishon Vijay Abraham I 

Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak 

> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
>  arch/arm/mach-omap2/cm2_7xx.h |4 ++
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   57 
> +
>  arch/arm/mach-omap2/prm7xx.h  |4 ++
>  3 files changed, 65 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
> index 9ad7594..e966e3a 100644
> --- a/arch/arm/mach-omap2/cm2_7xx.h
> +++ b/arch/arm/mach-omap2/cm2_7xx.h
> @@ -357,6 +357,10 @@
>  #define DRA7XX_CM_L3INIT_SATA_CLKCTRL
> DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
>  #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET  0x00a0
>  #define DRA7XX_CM_PCIE_STATICDEP_OFFSET  0x00a4
> +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET  0x00b0
> +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL 
> DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
> +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET  0x00b8
> +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL 
> DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
>  #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET  0x00c0
>  #define DRA7XX_CM_GMAC_STATICDEP_OFFSET  0x00c4
>  #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
> b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 3deb76e..6ff40a6 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>  };
>  
>  /*
> + * 'PCIE PHY' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
> + .name   = "pcie-phy",
> +};
> +
> +/* pcie1 phy */
> +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
> + .name   = "pcie1-phy",
> + .class  = _pcie_phy_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk   = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
> + .modulemode   = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 phy */
> +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
> + .name   = "pcie2-phy",
> + .class  = _pcie_phy_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk   = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
> + .modulemode   = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
>   * 'qspi' class
>   *
>   */
> @@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if 
> dra7xx_l4_cfg__ocp2scp1 = {
>   .user   = OCP_USER_MPU | OCP_USER_SDMA,
>  };
>  
> +/* l4_cfg -> pcie1 phy */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> + .master = _l4_cfg_hwmod,
> + .slave  = _pcie1_phy_hwmod,
> + .clk= "l4_root_clk_div",
> + .user   = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 phy */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
> + .master = _l4_cfg_hwmod,
> + .slave  = _pcie2_phy_hwmod,
> + .clk= "l4_root_clk_div",
> + .user   = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
>  static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
>   {
>   .pa_start   = 0x4b30,
> @@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
> __initdata = {
>   _l4_cfg__mpu,
>   _l4_cfg__ocp2scp1,
>   _l4_cfg__ocp2scp3,
> + _l4_cfg__pcie1_phy,
> + _l4_cfg__pcie2_phy,
>   _l3_main_1__qspi,
>   _l4_cfg__sata,
>   _l4_cfg__smartreflex_core,
> diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
> index d92a840..4bb50fbf 100644
> --- a/arch/arm/mach-omap2/prm7xx.h
> +++ b/arch/arm/mach-omap2/prm7xx.h
> @@ -374,6 +374,10 @@
>  #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET   0x007c
>  #define

Re: [PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-07-03 Thread Rajendra Nayak 
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
 Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
 Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
 for pcie1 phy and pcie2 phy.
 
 Cc: Tony Lindgren t...@atomide.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Paul Walmsley p...@pwsan.com
 Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
 Tested-by: Kishon Vijay Abraham I kis...@ti.com

Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak rna...@ti.com

 ---
 Please find the bootlog with these hwmod patches
 http://paste.ubuntu.com/7701601/
  arch/arm/mach-omap2/cm2_7xx.h |4 ++
  arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   57 
 +
  arch/arm/mach-omap2/prm7xx.h  |4 ++
  3 files changed, 65 insertions(+)
 
 diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
 index 9ad7594..e966e3a 100644
 --- a/arch/arm/mach-omap2/cm2_7xx.h
 +++ b/arch/arm/mach-omap2/cm2_7xx.h
 @@ -357,6 +357,10 @@
  #define DRA7XX_CM_L3INIT_SATA_CLKCTRL
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
  #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET  0x00a0
  #define DRA7XX_CM_PCIE_STATICDEP_OFFSET  0x00a4
 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET  0x00b0
 +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL 
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET  0x00b8
 +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL 
 DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
  #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET  0x00c0
  #define DRA7XX_CM_GMAC_STATICDEP_OFFSET  0x00c4
  #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
 diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
 b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 index 3deb76e..6ff40a6 100644
 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
 @@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  };
  
  /*
 + * 'PCIE PHY' class
 + *
 + */
 +
 +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
 + .name   = pcie-phy,
 +};
 +
 +/* pcie1 phy */
 +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
 + .name   = pcie1-phy,
 + .class  = dra7xx_pcie_phy_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
 + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/* pcie2 phy */
 +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
 + .name   = pcie2-phy,
 + .class  = dra7xx_pcie_phy_hwmod_class,
 + .clkdm_name = l3init_clkdm,
 + .main_clk   = l4_root_clk_div,
 + .prcm = {
 + .omap4 = {
 + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
 + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
 + .modulemode   = MODULEMODE_SWCTRL,
 + },
 + },
 +};
 +
 +/*
   * 'qspi' class
   *
   */
 @@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if 
 dra7xx_l4_cfg__ocp2scp1 = {
   .user   = OCP_USER_MPU | OCP_USER_SDMA,
  };
  
 +/* l4_cfg - pcie1 phy */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie1_phy_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
 +/* l4_cfg - pcie2 phy */
 +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
 + .master = dra7xx_l4_cfg_hwmod,
 + .slave  = dra7xx_pcie2_phy_hwmod,
 + .clk= l4_root_clk_div,
 + .user   = OCP_USER_MPU | OCP_USER_SDMA,
 +};
 +
  static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
   {
   .pa_start   = 0x4b30,
 @@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
 __initdata = {
   dra7xx_l4_cfg__mpu,
   dra7xx_l4_cfg__ocp2scp1,
   dra7xx_l4_cfg__ocp2scp3,
 + dra7xx_l4_cfg__pcie1_phy,
 + dra7xx_l4_cfg__pcie2_phy,
   dra7xx_l3_main_1__qspi,
   dra7xx_l4_cfg__sata,
   dra7xx_l4_cfg__smartreflex_core,
 diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
 index d92a840..4bb50fbf 100644
 --- a/arch/arm/mach-omap2/prm7xx.h
 +++ b/arch/arm/mach-omap2/prm7xx.h
 @@ -374,6 +374,10 @@
  #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET

[PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-06-25 Thread Kishon Vijay Abraham I 
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.

Cc: Tony Lindgren 
Cc: Russell King 
Cc: Paul Walmsley 
Signed-off-by: Kishon Vijay Abraham I 
Tested-by: Kishon Vijay Abraham I 
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
 arch/arm/mach-omap2/cm2_7xx.h |4 ++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   57 +
 arch/arm/mach-omap2/prm7xx.h  |4 ++
 3 files changed, 65 insertions(+)

diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
 #define DRA7XX_CM_L3INIT_SATA_CLKCTRL  
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
 #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL   
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL   
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
 #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET   0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3deb76e..6ff40a6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
 };
 
 /*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+   .name   = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+   .name   = "pcie1-phy",
+   .class  = _pcie_phy_hwmod_class,
+   .clkdm_name = "l3init_clkdm",
+   .main_clk   = "l4_root_clk_div",
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+   .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_SWCTRL,
+   },
+   },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+   .name   = "pcie2-phy",
+   .class  = _pcie_phy_hwmod_class,
+   .clkdm_name = "l3init_clkdm",
+   .main_clk   = "l4_root_clk_div",
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+   .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_SWCTRL,
+   },
+   },
+};
+
+/*
  * 'qspi' class
  *
  */
@@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 
= {
.user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+   .master = _l4_cfg_hwmod,
+   .slave  = _pcie1_phy_hwmod,
+   .clk= "l4_root_clk_div",
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+   .master = _l4_cfg_hwmod,
+   .slave  = _pcie2_phy_hwmod,
+   .clk= "l4_root_clk_div",
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start   = 0x4b30,
@@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
__initdata = {
_l4_cfg__mpu,
_l4_cfg__ocp2scp1,
_l4_cfg__ocp2scp3,
+   _l4_cfg__pcie1_phy,
+   _l4_cfg__pcie2_phy,
_l3_main_1__qspi,
_l4_cfg__sata,
_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET   0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET  0x00b0
+#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET0x00b4
+#define

[PATCH 1/2] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

2014-06-25 Thread Kishon Vijay Abraham I 
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.

Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Paul Walmsley p...@pwsan.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Tested-by: Kishon Vijay Abraham I kis...@ti.com
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
 arch/arm/mach-omap2/cm2_7xx.h |4 ++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |   57 +
 arch/arm/mach-omap2/prm7xx.h  |4 ++
 3 files changed, 65 insertions(+)

diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
 #define DRA7XX_CM_L3INIT_SATA_CLKCTRL  
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
 #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET0x00a0
 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL   
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL   
DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
 #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET0x00c0
 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET0x00c4
 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET   0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3deb76e..6ff40a6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
 };
 
 /*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+   .name   = pcie-phy,
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+   .name   = pcie1-phy,
+   .class  = dra7xx_pcie_phy_hwmod_class,
+   .clkdm_name = l3init_clkdm,
+   .main_clk   = l4_root_clk_div,
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+   .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_SWCTRL,
+   },
+   },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+   .name   = pcie2-phy,
+   .class  = dra7xx_pcie_phy_hwmod_class,
+   .clkdm_name = l3init_clkdm,
+   .main_clk   = l4_root_clk_div,
+   .prcm = {
+   .omap4 = {
+   .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+   .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+   .modulemode   = MODULEMODE_SWCTRL,
+   },
+   },
+};
+
+/*
  * 'qspi' class
  *
  */
@@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 
= {
.user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg - pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+   .master = dra7xx_l4_cfg_hwmod,
+   .slave  = dra7xx_pcie1_phy_hwmod,
+   .clk= l4_root_clk_div,
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg - pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+   .master = dra7xx_l4_cfg_hwmod,
+   .slave  = dra7xx_pcie2_phy_hwmod,
+   .clk= l4_root_clk_div,
+   .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start   = 0x4b30,
@@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] 
__initdata = {
dra7xx_l4_cfg__mpu,
dra7xx_l4_cfg__ocp2scp1,
dra7xx_l4_cfg__ocp2scp3,
+   dra7xx_l4_cfg__pcie1_phy,
+   dra7xx_l4_cfg__pcie2_phy,
dra7xx_l3_main_1__qspi,
dra7xx_l4_cfg__sata,
dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET   0x008c
+#define