Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU
On Wed, Jun 3, 2020 at 5:42 PM 李扬韬 wrote:
>
> >> + /* Enable the lock bits on all PLLs */
> >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
> >> + val = readl(reg + pll_regs[i]);
> >> + val |= BIT(29);
> >
> >Having a define for that would be nice here
> >
> >> + writel(val, reg + pll_regs[i]);
> >> + }
> >> +
> >> + /*
> >> + * In order to pass the EMI certification, the SDM function of
> >> + * the peripheral 1 bus is enabled, and the frequency is still
> >> + * calculated using the previous division factor.
> >> + */
> >> + writel(0xd130, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
> >
> >Same here
>
> Having a define? I don’t quite understand what you mean,
> can you give me an example?
What Maxime means is that 0xd130 is a magic number.
It is better to make a properly named macro, or many macros
that you then bitwise-OR together. So you should make macros
for each bitfield in that register, which would likely include
the SDM calculation factors, the enable bit, and any other fields.
ChenYu
> MBR,
> Yangtao
回复：[PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU
>> + /* Enable the lock bits on all PLLs */
>> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
>> + val = readl(reg + pll_regs[i]);
>> + val |= BIT(29);
>
>Having a define for that would be nice here
>
>> + writel(val, reg + pll_regs[i]);
>> + }
>> +
>> + /*
>> + * In order to pass the EMI certification, the SDM function of
>> + * the peripheral 1 bus is enabled, and the frequency is still
>> + * calculated using the previous division factor.
>> + */
>> + writel(0xd130, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG);
>
>Same here
Having a define? I don’t quite understand what you mean,
can you give me an example?
MBR,
Yangtao
Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU
Hi,
On Fri, May 22, 2020 at 11:07:40AM +0800, Frank Lee wrote:
> Add support for a100 in the sunxi-ng CCU framework.
>
> Signed-off-by: Frank Lee
> ---
> drivers/clk/sunxi-ng/Kconfig | 10 +
> drivers/clk/sunxi-ng/Makefile |2 +
> drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 206 +++
> drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 14 +
> drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1255 +
> drivers/clk/sunxi-ng/ccu-sun50i-a100.h| 14 +
> include/dt-bindings/clock/sun50i-a100-ccu.h | 141 ++
> include/dt-bindings/clock/sun50i-a100-r-ccu.h | 25 +
> include/dt-bindings/reset/sun50i-a100-ccu.h | 68 +
> include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 +
> 10 files changed, 1753 insertions(+)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
> create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
> create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index cdf333003c30..ce5f5847d5d3 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -17,6 +17,16 @@ config SUN50I_A64_CCU
> default ARM64 && ARCH_SUNXI
> depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
>
> +config SUN50I_A100_CCU
> + bool "Support for the Allwinner A100 CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
> +config SUN50I_A100_R_CCU
> + bool "Support for the Allwinner A100 PRCM CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> +
> config SUN50I_H6_CCU
> bool "Support for the Allwinner H6 CCU"
> default ARM64 && ARCH_SUNXI
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 4c7bee883f2f..3eb5cff40eac 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -23,6 +23,8 @@ obj-y += ccu_mp.o
> # SoC support
> obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
> obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
> +obj-$(CONFIG_SUN50I_A100_CCU)+= ccu-sun50i-a100.o
> +obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o
> obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
> obj-$(CONFIG_SUN50I_H6_R_CCU)+= ccu-sun50i-h6-r.o
> obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
> new file mode 100644
> index ..31875269ef90
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Frank Lee
The domain doesn't match the one used to send that patch, is that intentional?
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_nm.h"
> +
> +#include "ccu-sun50i-a100-r.h"
> +
> +static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
> + "iosc", "pll-periph0" };
> +static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
> + { .index = 3, .shift = 0, .width = 5 },
> +};
> +
> +static struct ccu_div cpus_clk = {
> + .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
> +
> + .mux= {
> + .shift = 24,
> + .width = 2,
> +
> + .var_predivs= cpus_r_apb2_predivs,
> + .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
> + },
> +
> + .common = {
> + .reg= 0x000,
> + .features = CCU_FEATURE_VARIABLE_PREDIV,
> + .hw.init= CLK_HW_INIT_PARENTS("cpus",
> + cpus_r_apb2_parents,
> + _div_ops,
> + 0),
> + },
> +};
> +
> +static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", _clk.common.hw, 1, 1, 0);
> +
> +static struct ccu_div r_apb1_clk = {
> + .div= _SUNXI_CCU_DIV(0, 2),
> +
> + .common = {
> + .reg= 0x00c,
> + .hw.init= CLK_HW_INIT("r-apb1",
> + "r-ahb",
> + _div_ops,
> + 0),
> + },
> +};
> +
> +static struct
[PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU
Add support for a100 in the sunxi-ng CCU framework.
Signed-off-by: Frank Lee
---
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile |2 +
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 206 +++
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 14 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.c| 1255 +
drivers/clk/sunxi-ng/ccu-sun50i-a100.h| 14 +
include/dt-bindings/clock/sun50i-a100-ccu.h | 141 ++
include/dt-bindings/clock/sun50i-a100-r-ccu.h | 25 +
include/dt-bindings/reset/sun50i-a100-ccu.h | 68 +
include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 +
10 files changed, 1753 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h
create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index cdf333003c30..ce5f5847d5d3 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -17,6 +17,16 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_A100_CCU
+ bool "Support for the Allwinner A100 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
+config SUN50I_A100_R_CCU
+ bool "Support for the Allwinner A100 PRCM CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_CCU
bool "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 4c7bee883f2f..3eb5cff40eac 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,6 +23,8 @@ obj-y += ccu_mp.o
# SoC support
obj-$(CONFIG_SUNIV_F1C100S_CCU)+= ccu-suniv-f1c100s.o
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
+obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
+obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
new file mode 100644
index ..31875269ef90
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Frank Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-a100-r.h"
+
+static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
+"iosc", "pll-periph0" };
+static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
+ { .index = 3, .shift = 0, .width = 5 },
+};
+
+static struct ccu_div cpus_clk = {
+ .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux= {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs= cpus_r_apb2_predivs,
+ .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
+ },
+
+ .common = {
+ .reg= 0x000,
+ .features = CCU_FEATURE_VARIABLE_PREDIV,
+ .hw.init= CLK_HW_INIT_PARENTS("cpus",
+ cpus_r_apb2_parents,
+ _div_ops,
+ 0),
+ },
+};
+
+static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", _clk.common.hw, 1, 1, 0);
+
+static struct ccu_div r_apb1_clk = {
+ .div= _SUNXI_CCU_DIV(0, 2),
+
+ .common = {
+ .reg= 0x00c,
+ .hw.init= CLK_HW_INIT("r-apb1",
+ "r-ahb",
+ _div_ops,
+ 0),
+ },
+};
+
+static struct ccu_div r_apb2_clk = {
+ .div= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+ .mux= {
+ .shift = 24,
+ .width = 2,
+
+ .var_predivs= cpus_r_apb2_predivs,
+ .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
+ },
+
+
