RE: [EXT] Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
Hi Lorenzo,
Thanks a lot for your comments, I am waiting for this patches approve of
http://patchwork.ozlabs.org/project/linux-pci/list/?series=102378, and once
these patches approved, I will resent the patches base on the latest base.
Best regards
Xiaowei
-Original Message-
From: Lorenzo Pieralisi
Sent: 2019年4月25日 19:32
To: Xiaowei Bao
Cc: bhelg...@google.com; Z.q. Hou ; robh...@kernel.org;
mark.rutl...@arm.com; shawn...@kernel.org; Leo Li ;
kis...@ti.com; gre...@linuxfoundation.org; l.subrahma...@mobiveil.co.in;
a...@arndb.de; M.h. Lian ; linux-...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
linux-kernel@vger.kernel.org
Subject: [EXT] Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
Caution: EXT Email
On Mon, Feb 18, 2019 at 05:46:38PM +0800, Xiaowei Bao wrote:
> Add the EP mode support for Mobiveil base on endpoint framework.
>
> Signed-off-by: Xiaowei Bao
> ---
> depends on:
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
> work.ozlabs.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D88754d
> ata=02%7C01%7Cxiaowei.bao%40nxp.com%7C52755aabae3a4cca65ba08d6c971a7de
> %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636917887360279903s
> data=9nw%2BwVKx11937Vh5ShwQNX97QzC3q9PJVTCQsbFbfjc%3Dreserved=0
You will have to rebase it on top of the updated series:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fuser%2Ftodo%2Flinux-pci%2F%3Fseries%3D102378data=02%7C01%7Cxiaowei.bao%40nxp.com%7C52755aabae3a4cca65ba08d6c971a7de%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636917887360279903sdata=vqpwdXMzTtc4Uf2vt3vHxOL5PlHHYY%2F3Dsfj7CIsJfc%3Dreserved=0
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fuser%2Ftodo%2Flinux-pci%2F%3Fseries%3D102396data=02%7C01%7Cxiaowei.bao%40nxp.com%7C52755aabae3a4cca65ba08d6c971a7de%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636917887360279903sdata=D%2F5cTIiBy5CHU4K7K7n6GHcFlrt6RV%2Ff9jsjx8bmaY4%3Dreserved=0
I will mark it as superseded in patchwork, thanks.
Lorenzo
> drivers/pci/controller/mobiveil/Kconfig|5 +
> drivers/pci/controller/mobiveil/Makefile |1 +
> drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 527
>
> drivers/pci/controller/mobiveil/pcie-mobiveil.c| 100 -
> drivers/pci/controller/mobiveil/pcie-mobiveil.h| 64 +++
> 5 files changed, 691 insertions(+), 6 deletions(-) create mode
> 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> index 3ddb7d6..c037db6 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_MOBIVEIL
>
> +config PCIE_MOBIVEIL_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_MOBIVEIL
> +
> config PCIE_MOBIVEIL_PLAT
> bool "Mobiveil AXI PCIe controller"
> depends on ARCH_ZYNQMP || COMPILE_TEST diff --git
> a/drivers/pci/controller/mobiveil/Makefile
> b/drivers/pci/controller/mobiveil/Makefile
> index ff66774..4f520b7 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
> obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o diff --git
> a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> new file mode 100644
> index 000..16ca7fb
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> @@ -0,0 +1,527 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * Mobiveil PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + * Author: Xiaowei Bao */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "pcie-mobiveil.h"
> +
> +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep) {
> + struct pci_epc *epc = ep->epc;
> +
> + pci_epc_linkup(epc);
> +}
> +
> +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> + enum pci_barno bar) {
> + csr_writel(pcie, bar, GPEX_BAR_SELECT);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW); }
> +
> +void mobiveil_pcie_ep_reset_bar(struct
Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
On Mon, Feb 18, 2019 at 05:46:38PM +0800, Xiaowei Bao wrote:
> Add the EP mode support for Mobiveil base on endpoint framework.
>
> Signed-off-by: Xiaowei Bao
> ---
> depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=88754
You will have to rebase it on top of the updated series:
https://patchwork.ozlabs.org/user/todo/linux-pci/?series=102378
https://patchwork.ozlabs.org/user/todo/linux-pci/?series=102396
I will mark it as superseded in patchwork, thanks.
Lorenzo
> drivers/pci/controller/mobiveil/Kconfig|5 +
> drivers/pci/controller/mobiveil/Makefile |1 +
> drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 527
>
> drivers/pci/controller/mobiveil/pcie-mobiveil.c| 100 -
> drivers/pci/controller/mobiveil/pcie-mobiveil.h| 64 +++
> 5 files changed, 691 insertions(+), 6 deletions(-)
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> index 3ddb7d6..c037db6 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_MOBIVEIL
>
> +config PCIE_MOBIVEIL_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_MOBIVEIL
> +
> config PCIE_MOBIVEIL_PLAT
> bool "Mobiveil AXI PCIe controller"
> depends on ARCH_ZYNQMP || COMPILE_TEST
> diff --git a/drivers/pci/controller/mobiveil/Makefile
> b/drivers/pci/controller/mobiveil/Makefile
> index ff66774..4f520b7 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
> obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> new file mode 100644
> index 000..16ca7fb
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> @@ -0,0 +1,527 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * Mobiveil PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + * Author: Xiaowei Bao
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "pcie-mobiveil.h"
> +
> +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> +
> + pci_epc_linkup(epc);
> +}
> +
> +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> + enum pci_barno bar)
> +{
> + csr_writel(pcie, bar, GPEX_BAR_SELECT);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
> +}
> +
> +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> + enum pci_barno bar)
> +{
> + __mobiveil_pcie_ep_reset_bar(pcie, bar);
> +}
> +
> +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
> +u8 cap_ptr, u8 cap)
> +{
> + u8 cap_id, next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, cap_ptr);
> + next_cap_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> +
> + if (cap_id == cap)
> + return cap_ptr;
> +
> + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
> + return 0;
> +
> + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
> +}
> +
> +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
> +u8 cap)
> +{
> + u8 next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
> + next_cap_ptr = (reg & 0x00ff);
> +
> + if (!next_cap_ptr)
> + return 0;
> +
> + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
> +}
> +
> +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
> + struct pci_epf_header *hdr)
> +{
> + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
> + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
> +
> + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
> + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
> + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
> + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
> + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
> +PCI_CLASS_DEVICE);
> + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
> + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
> +
RE: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
-Original Message-
From: Subrahmanya Lingappa
Sent: 2019年3月8日 14:45
To: Xiaowei Bao
Cc: Bjorn Helgaas ; Z.q. Hou ;
robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
; kis...@ti.com; Lorenzo Pieralisi
; gre...@linuxfoundation.org; a...@arndb.de; M.h.
Lian ; linux-...@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
Xiaowei,
On Mon, Feb 18, 2019 at 3:22 PM Xiaowei Bao wrote:
>
> Add the EP mode support for Mobiveil base on endpoint framework.
>
> Signed-off-by: Xiaowei Bao
> ---
> depends on:
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatc
> hwork.ozlabs.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D88754
> data=02%7C01%7Cxiaowei.bao%40nxp.com%7C81bba6e6911b4c04fb0808d6a3910ce
> e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636876240720287700
> sdata=i2gZUXQxRPr8R82KOuBDZZWiaKJBtXYwB9JV7SwHTXY%3Dreserved=0
>
> drivers/pci/controller/mobiveil/Kconfig|5 +
> drivers/pci/controller/mobiveil/Makefile |1 +
> drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 527
>
> drivers/pci/controller/mobiveil/pcie-mobiveil.c| 100 -
> drivers/pci/controller/mobiveil/pcie-mobiveil.h| 64 +++
> 5 files changed, 691 insertions(+), 6 deletions(-) create mode
> 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> index 3ddb7d6..c037db6 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_MOBIVEIL
>
> +config PCIE_MOBIVEIL_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_MOBIVEIL
> +
> config PCIE_MOBIVEIL_PLAT
> bool "Mobiveil AXI PCIe controller"
> depends on ARCH_ZYNQMP || COMPILE_TEST diff --git
> a/drivers/pci/controller/mobiveil/Makefile
> b/drivers/pci/controller/mobiveil/Makefile
> index ff66774..4f520b7 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
> obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o diff --git
> a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> new file mode 100644
> index 000..16ca7fb
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> @@ -0,0 +1,527 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * Mobiveil PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + * Author: Xiaowei Bao */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "pcie-mobiveil.h"
> +
> +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep) {
> + struct pci_epc *epc = ep->epc;
> +
> + pci_epc_linkup(epc);
> +}
> +
> +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> +enum pci_barno bar) {
> + csr_writel(pcie, bar, GPEX_BAR_SELECT);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW); }
> +
> +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> + enum pci_barno bar) {
> + __mobiveil_pcie_ep_reset_bar(pcie, bar); }
> +
> +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
> + u8 cap_ptr, u8 cap) {
> + u8 cap_id, next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, cap_ptr);
> + next_cap_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> +
> + if (cap_id == cap)
> + return cap_ptr;
> +
> + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
> + return 0;
> +
> + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr,
> +cap); }
> +
> +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
> + u8 cap) {
> + u8 next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
> + next_cap_ptr =
Re: [PATCH 1/6] PCI: mobiveil: Add the EP mode support
Xiaowei,
On Mon, Feb 18, 2019 at 3:22 PM Xiaowei Bao wrote:
>
> Add the EP mode support for Mobiveil base on endpoint framework.
>
> Signed-off-by: Xiaowei Bao
> ---
> depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=88754
>
> drivers/pci/controller/mobiveil/Kconfig|5 +
> drivers/pci/controller/mobiveil/Makefile |1 +
> drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 527
>
> drivers/pci/controller/mobiveil/pcie-mobiveil.c| 100 -
> drivers/pci/controller/mobiveil/pcie-mobiveil.h| 64 +++
> 5 files changed, 691 insertions(+), 6 deletions(-)
> create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
>
> diff --git a/drivers/pci/controller/mobiveil/Kconfig
> b/drivers/pci/controller/mobiveil/Kconfig
> index 3ddb7d6..c037db6 100644
> --- a/drivers/pci/controller/mobiveil/Kconfig
> +++ b/drivers/pci/controller/mobiveil/Kconfig
> @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
> depends on PCI_MSI_IRQ_DOMAIN
> select PCIE_MOBIVEIL
>
> +config PCIE_MOBIVEIL_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_MOBIVEIL
> +
> config PCIE_MOBIVEIL_PLAT
> bool "Mobiveil AXI PCIe controller"
> depends on ARCH_ZYNQMP || COMPILE_TEST
> diff --git a/drivers/pci/controller/mobiveil/Makefile
> b/drivers/pci/controller/mobiveil/Makefile
> index ff66774..4f520b7 100644
> --- a/drivers/pci/controller/mobiveil/Makefile
> +++ b/drivers/pci/controller/mobiveil/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
> +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
> obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
> obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> new file mode 100644
> index 000..16ca7fb
> --- /dev/null
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
> @@ -0,0 +1,527 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * Mobiveil PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + * Author: Xiaowei Bao
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include "pcie-mobiveil.h"
> +
> +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> +
> + pci_epc_linkup(epc);
> +}
> +
> +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> +enum pci_barno bar)
> +{
> + csr_writel(pcie, bar, GPEX_BAR_SELECT);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
> + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
> +}
> +
> +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
> + enum pci_barno bar)
> +{
> + __mobiveil_pcie_ep_reset_bar(pcie, bar);
> +}
> +
> +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
> + u8 cap_ptr, u8 cap)
> +{
> + u8 cap_id, next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, cap_ptr);
> + next_cap_ptr = (reg & 0xff00) >> 8;
> + cap_id = (reg & 0x00ff);
> +
> + if (cap_id == cap)
> + return cap_ptr;
> +
> + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
> + return 0;
> +
> + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
> +}
> +
> +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
> + u8 cap)
> +{
> + u8 next_cap_ptr;
> + u16 reg;
> +
> + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
> + next_cap_ptr = (reg & 0x00ff);
> +
> + if (!next_cap_ptr)
> + return 0;
> +
> + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
> +}
> +
> +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
> +struct pci_epf_header *hdr)
> +{
> + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
> + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
> +
> + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
> + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
> + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
> + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
> + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
> + PCI_CLASS_DEVICE);
> + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
> + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
> + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
> + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
> +
> + return 0;
> +}
> +
> +static
[PATCH 1/6] PCI: mobiveil: Add the EP mode support
Add the EP mode support for Mobiveil base on endpoint framework.
Signed-off-by: Xiaowei Bao
---
depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=88754
drivers/pci/controller/mobiveil/Kconfig|5 +
drivers/pci/controller/mobiveil/Makefile |1 +
drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 527
drivers/pci/controller/mobiveil/pcie-mobiveil.c| 100 -
drivers/pci/controller/mobiveil/pcie-mobiveil.h| 64 +++
5 files changed, 691 insertions(+), 6 deletions(-)
create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
diff --git a/drivers/pci/controller/mobiveil/Kconfig
b/drivers/pci/controller/mobiveil/Kconfig
index 3ddb7d6..c037db6 100644
--- a/drivers/pci/controller/mobiveil/Kconfig
+++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_MOBIVEIL
+config PCIE_MOBIVEIL_EP
+ bool
+ depends on PCI_ENDPOINT
+ select PCIE_MOBIVEIL
+
config PCIE_MOBIVEIL_PLAT
bool "Mobiveil AXI PCIe controller"
depends on ARCH_ZYNQMP || COMPILE_TEST
diff --git a/drivers/pci/controller/mobiveil/Makefile
b/drivers/pci/controller/mobiveil/Makefile
index ff66774..4f520b7 100644
--- a/drivers/pci/controller/mobiveil/Makefile
+++ b/drivers/pci/controller/mobiveil/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
+obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
new file mode 100644
index 000..16ca7fb
--- /dev/null
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * Mobiveil PCIe Endpoint controller driver
+ *
+ * Copyright (C) 2018 NXP Semiconductor.
+ * Author: Xiaowei Bao
+ */
+
+#include
+#include
+#include
+#include
+#include "pcie-mobiveil.h"
+
+void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
+{
+ struct pci_epc *epc = ep->epc;
+
+ pci_epc_linkup(epc);
+}
+
+static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
+enum pci_barno bar)
+{
+ csr_writel(pcie, bar, GPEX_BAR_SELECT);
+ csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
+ csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
+}
+
+void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
+ enum pci_barno bar)
+{
+ __mobiveil_pcie_ep_reset_bar(pcie, bar);
+}
+
+static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
+ u8 cap_ptr, u8 cap)
+{
+ u8 cap_id, next_cap_ptr;
+ u16 reg;
+
+ reg = csr_readw(pcie, cap_ptr);
+ next_cap_ptr = (reg & 0xff00) >> 8;
+ cap_id = (reg & 0x00ff);
+
+ if (cap_id == cap)
+ return cap_ptr;
+
+ if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
+ return 0;
+
+ return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
+}
+
+static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
+ u8 cap)
+{
+ u8 next_cap_ptr;
+ u16 reg;
+
+ reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
+ next_cap_ptr = (reg & 0x00ff);
+
+ if (!next_cap_ptr)
+ return 0;
+
+ return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
+}
+
+static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
+struct pci_epf_header *hdr)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
+ csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
+ csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
+ csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
+ csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
+ PCI_CLASS_DEVICE);
+ csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
+ csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
+ csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
+ csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
+
+ return 0;
+}
+
+static int mobiveil_pcie_ep_inbound_atu(struct mobiveil_pcie_ep *ep,
+ u8 func_no, enum pci_barno bar,
+ dma_addr_t cpu_addr)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
+
+
