Re: [PATCH 10/10] atl1: reduce forward declarations
applied 1-10 to #upstream (2.6.26) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 10/10] atl1: reduce forward declarations
applied 1-10 to #upstream (2.6.26) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 10/10] atl1: reduce forward declarations
Rearrange functions to allow removal of some forward declarations.
Make certain global functions static along the way.
Signed-off-by: Jay Cliburn <[EMAIL PROTECTED]>
Acked-by: Chris Snook <[EMAIL PROTECTED]>
---
drivers/net/atlx/atl1.c | 1406 +++---
drivers/net/atlx/atl1.h | 10 -
2 files changed, 703 insertions(+), 713 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 6f4a1d5..240db84 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -108,6 +108,709 @@ module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
/*
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ * hw - Struct containing variables accessed by shared code
+ * return : 0 or idle status (if error)
+ */
+static s32 atl1_reset_hw(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw->back->pdev;
+ struct atl1_adapter *adapter = hw->back;
+ u32 icr;
+ int i;
+
+ /*
+* Clear Interrupt mask to stop board from generating
+* interrupts & Clear any pending interrupt events
+*/
+ /*
+* iowrite32(0, hw->hw_addr + REG_IMR);
+* iowrite32(0x, hw->hw_addr + REG_ISR);
+*/
+
+ /*
+* Issue Soft Reset to the MAC. This will reset the chip's
+* transmit, receive, DMA. It will not effect
+* the current PCI configuration. The global reset bit is self-
+* clearing, and should clear within a microsecond.
+*/
+ iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
+ ioread32(hw->hw_addr + REG_MASTER_CTRL);
+
+ iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
+ ioread16(hw->hw_addr + REG_PHY_ENABLE);
+
+ /* delay about 1ms */
+ msleep(1);
+
+ /* Wait at least 10ms for All module to be Idle */
+ for (i = 0; i < 10; i++) {
+ icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
+ if (!icr)
+ break;
+ /* delay 1 ms */
+ msleep(1);
+ /* FIXME: still the right way to do this? */
+ cpu_relax();
+ }
+
+ if (icr) {
+ if (netif_msg_hw(adapter))
+ dev_dbg(>dev, "ICR = 0x%x\n", icr);
+ return icr;
+ }
+
+ return 0;
+}
+
+/* function about EEPROM
+ *
+ * check_eeprom_exist
+ * return 0 if eeprom exist
+ */
+static int atl1_check_eeprom_exist(struct atl1_hw *hw)
+{
+ u32 value;
+ value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
+ if (value & SPI_FLASH_CTRL_EN_VPD) {
+ value &= ~SPI_FLASH_CTRL_EN_VPD;
+ iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
+ }
+
+ value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
+ return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
+}
+
+static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
+{
+ int i;
+ u32 control;
+
+ if (offset & 3)
+ /* address do not align */
+ return false;
+
+ iowrite32(0, hw->hw_addr + REG_VPD_DATA);
+ control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
+ iowrite32(control, hw->hw_addr + REG_VPD_CAP);
+ ioread32(hw->hw_addr + REG_VPD_CAP);
+
+ for (i = 0; i < 10; i++) {
+ msleep(2);
+ control = ioread32(hw->hw_addr + REG_VPD_CAP);
+ if (control & VPD_CAP_VPD_FLAG)
+ break;
+ }
+ if (control & VPD_CAP_VPD_FLAG) {
+ *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
+ return true;
+ }
+ /* timeout */
+ return false;
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ u32 val;
+ int i;
+
+ val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
+ MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
+ MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
+ ioread32(hw->hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
+ if (!(val & (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (!(val & (MDIO_START | MDIO_BUSY))) {
+ *phy_data = (u16) val;
+ return 0;
+ }
+ return ATLX_ERR_PHY;
+}
+
+#define CUSTOM_SPI_CS_SETUP2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
+static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
+{
+ int i;
+ u32
[PATCH 10/10] atl1: reduce forward declarations
Rearrange functions to allow removal of some forward declarations.
Make certain global functions static along the way.
Signed-off-by: Jay Cliburn [EMAIL PROTECTED]
Acked-by: Chris Snook [EMAIL PROTECTED]
---
drivers/net/atlx/atl1.c | 1406 +++---
drivers/net/atlx/atl1.h | 10 -
2 files changed, 703 insertions(+), 713 deletions(-)
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 6f4a1d5..240db84 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -108,6 +108,709 @@ module_param(debug, int, 0);
MODULE_PARM_DESC(debug, Message level (0=none,...,16=all));
/*
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ * hw - Struct containing variables accessed by shared code
+ * return : 0 or idle status (if error)
+ */
+static s32 atl1_reset_hw(struct atl1_hw *hw)
+{
+ struct pci_dev *pdev = hw-back-pdev;
+ struct atl1_adapter *adapter = hw-back;
+ u32 icr;
+ int i;
+
+ /*
+* Clear Interrupt mask to stop board from generating
+* interrupts Clear any pending interrupt events
+*/
+ /*
+* iowrite32(0, hw-hw_addr + REG_IMR);
+* iowrite32(0x, hw-hw_addr + REG_ISR);
+*/
+
+ /*
+* Issue Soft Reset to the MAC. This will reset the chip's
+* transmit, receive, DMA. It will not effect
+* the current PCI configuration. The global reset bit is self-
+* clearing, and should clear within a microsecond.
+*/
+ iowrite32(MASTER_CTRL_SOFT_RST, hw-hw_addr + REG_MASTER_CTRL);
+ ioread32(hw-hw_addr + REG_MASTER_CTRL);
+
+ iowrite16(1, hw-hw_addr + REG_PHY_ENABLE);
+ ioread16(hw-hw_addr + REG_PHY_ENABLE);
+
+ /* delay about 1ms */
+ msleep(1);
+
+ /* Wait at least 10ms for All module to be Idle */
+ for (i = 0; i 10; i++) {
+ icr = ioread32(hw-hw_addr + REG_IDLE_STATUS);
+ if (!icr)
+ break;
+ /* delay 1 ms */
+ msleep(1);
+ /* FIXME: still the right way to do this? */
+ cpu_relax();
+ }
+
+ if (icr) {
+ if (netif_msg_hw(adapter))
+ dev_dbg(pdev-dev, ICR = 0x%x\n, icr);
+ return icr;
+ }
+
+ return 0;
+}
+
+/* function about EEPROM
+ *
+ * check_eeprom_exist
+ * return 0 if eeprom exist
+ */
+static int atl1_check_eeprom_exist(struct atl1_hw *hw)
+{
+ u32 value;
+ value = ioread32(hw-hw_addr + REG_SPI_FLASH_CTRL);
+ if (value SPI_FLASH_CTRL_EN_VPD) {
+ value = ~SPI_FLASH_CTRL_EN_VPD;
+ iowrite32(value, hw-hw_addr + REG_SPI_FLASH_CTRL);
+ }
+
+ value = ioread16(hw-hw_addr + REG_PCIE_CAP_LIST);
+ return ((value 0xFF00) == 0x6C00) ? 0 : 1;
+}
+
+static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
+{
+ int i;
+ u32 control;
+
+ if (offset 3)
+ /* address do not align */
+ return false;
+
+ iowrite32(0, hw-hw_addr + REG_VPD_DATA);
+ control = (offset VPD_CAP_VPD_ADDR_MASK) VPD_CAP_VPD_ADDR_SHIFT;
+ iowrite32(control, hw-hw_addr + REG_VPD_CAP);
+ ioread32(hw-hw_addr + REG_VPD_CAP);
+
+ for (i = 0; i 10; i++) {
+ msleep(2);
+ control = ioread32(hw-hw_addr + REG_VPD_CAP);
+ if (control VPD_CAP_VPD_FLAG)
+ break;
+ }
+ if (control VPD_CAP_VPD_FLAG) {
+ *p_value = ioread32(hw-hw_addr + REG_VPD_DATA);
+ return true;
+ }
+ /* timeout */
+ return false;
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ u32 val;
+ int i;
+
+ val = ((u32) (reg_addr MDIO_REG_ADDR_MASK)) MDIO_REG_ADDR_SHIFT |
+ MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4
+ MDIO_CLK_SEL_SHIFT;
+ iowrite32(val, hw-hw_addr + REG_MDIO_CTRL);
+ ioread32(hw-hw_addr + REG_MDIO_CTRL);
+
+ for (i = 0; i MDIO_WAIT_TIMES; i++) {
+ udelay(2);
+ val = ioread32(hw-hw_addr + REG_MDIO_CTRL);
+ if (!(val (MDIO_START | MDIO_BUSY)))
+ break;
+ }
+ if (!(val (MDIO_START | MDIO_BUSY))) {
+ *phy_data = (u16) val;
+ return 0;
+ }
+ return ATLX_ERR_PHY;
+}
+
+#define CUSTOM_SPI_CS_SETUP2
+#define CUSTOM_SPI_CLK_HI 2
+#define CUSTOM_SPI_CLK_LO 2
+#define CUSTOM_SPI_CS_HOLD 2
+#define CUSTOM_SPI_CS_HI 3
+
+static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
+{
+ int i;
+ u32 value;
+
+ iowrite32(0, hw-hw_addr +
