Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-07-17 Thread Abhishek Sahu 

On 2017-07-04 15:25, Archit Taneja wrote:

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:

The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 136 
+++---

  1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c 
b/drivers/mtd/nand/qcom_nandc.c

index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
  #include 
  #include 

-/* NANDc reg offsets */
-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
  /* NAND_FLASH_CMD bits */
  #define   PAGE_ACCBIT(4)
  #define   LAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
  #define QPIC_PER_CW_MAX_CMD_SGL   (32)
  #define QPIC_PER_CW_MAX_DATA_SGL  (8)

+/* NANDc reg offsets enumeration */
+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
  /*
   * This data type corresponds to the BAM transaction which will be 
used for all

   * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
   *bam dma
   * @max_cwperpage:maximum qpic codeword required. calcualted
   *from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {

u32 cmd1, vld;
u32 ecc_modes;
+   const u32 *regs_offsets;


minor quirk:

s/regs_offsets/reg_offsets



 Sure. I will fix this in v2.


  };

  /*
@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
  };

+/* Mapping table which contains the actual register offsets */
+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+

Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-07-17 Thread Abhishek Sahu 

On 2017-07-04 15:25, Archit Taneja wrote:

On 06/29/2017 12:46 PM, Abhishek Sahu wrote:

The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 136 
+++---

  1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c 
b/drivers/mtd/nand/qcom_nandc.c

index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
  #include 
  #include 

-/* NANDc reg offsets */
-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
  /* NAND_FLASH_CMD bits */
  #define   PAGE_ACCBIT(4)
  #define   LAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
  #define QPIC_PER_CW_MAX_CMD_SGL   (32)
  #define QPIC_PER_CW_MAX_DATA_SGL  (8)

+/* NANDc reg offsets enumeration */
+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
  /*
   * This data type corresponds to the BAM transaction which will be 
used for all

   * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
   *bam dma
   * @max_cwperpage:maximum qpic codeword required. calcualted
   *from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {

u32 cmd1, vld;
u32 ecc_modes;
+   const u32 *regs_offsets;


minor quirk:

s/regs_offsets/reg_offsets



 Sure. I will fix this in v2.


  };

  /*
@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
  };

+/* Mapping table which contains the actual register offsets */
+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+   [NAND_EXEC_CMD] = 0x10,
+

Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-07-04 Thread Archit Taneja 



On 06/29/2017 12:46 PM, Abhishek Sahu wrote:

The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 136 +++---
  1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
  #include 
  #include 
  
-/* NANDc reg offsets */

-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
  /* NAND_FLASH_CMD bits */
  #define   PAGE_ACCBIT(4)
  #define   LAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
  #define QPIC_PER_CW_MAX_CMD_SGL   (32)
  #define QPIC_PER_CW_MAX_DATA_SGL  (8)
  
+/* NANDc reg offsets enumeration */

+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
  /*
   * This data type corresponds to the BAM transaction which will be used for 
all
   * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
   *bam dma
   * @max_cwperpage:maximum qpic codeword required. calcualted
   *from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {
  
  	u32 cmd1, vld;

u32 ecc_modes;
+   const u32 *regs_offsets;


minor quirk:

s/regs_offsets/reg_offsets


  };
  
  /*

@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
  };
  
+/* Mapping table which contains the actual register offsets */

+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+   [NAND_EXEC_CMD] = 0x10,
+   [NAND_FLASH_STATUS] = 0x14,
+

Re: [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-07-04 Thread Archit Taneja 



On 06/29/2017 12:46 PM, Abhishek Sahu wrote:

The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
  drivers/mtd/nand/qcom_nandc.c | 136 +++---
  1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
  #include 
  #include 
  
-/* NANDc reg offsets */

-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
  /* NAND_FLASH_CMD bits */
  #define   PAGE_ACCBIT(4)
  #define   LAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
  #define QPIC_PER_CW_MAX_CMD_SGL   (32)
  #define QPIC_PER_CW_MAX_DATA_SGL  (8)
  
+/* NANDc reg offsets enumeration */

+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
  /*
   * This data type corresponds to the BAM transaction which will be used for 
all
   * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
   *bam dma
   * @max_cwperpage:maximum qpic codeword required. calcualted
   *from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
   */
  struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {
  
  	u32 cmd1, vld;

u32 ecc_modes;
+   const u32 *regs_offsets;


minor quirk:

s/regs_offsets/reg_offsets


  };
  
  /*

@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
  };
  
+/* Mapping table which contains the actual register offsets */

+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+   [NAND_EXEC_CMD] = 0x10,
+   [NAND_FLASH_STATUS] = 0x14,
+   [NAND_BUFFER_STATUS] = 0x18,
+

[PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-06-29 Thread Abhishek Sahu 
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
 drivers/mtd/nand/qcom_nandc.c | 136 +++---
 1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
 #include 
 #include 
 
-/* NANDc reg offsets */
-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
 /* NAND_FLASH_CMD bits */
 #definePAGE_ACCBIT(4)
 #defineLAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
 #define QPIC_PER_CW_MAX_CMD_SGL(32)
 #define QPIC_PER_CW_MAX_DATA_SGL   (8)
 
+/* NANDc reg offsets enumeration */
+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
 /*
  * This data type corresponds to the BAM transaction which will be used for all
  * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
  * bam dma
  * @max_cwperpage: maximum qpic codeword required. calcualted
  * from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
  */
 struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {
 
u32 cmd1, vld;
u32 ecc_modes;
+   const u32 *regs_offsets;
 };
 
 /*
@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
 };
 
+/* Mapping table which contains the actual register offsets */
+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+   [NAND_EXEC_CMD] = 0x10,
+   [NAND_FLASH_STATUS] = 0x14,
+   [NAND_BUFFER_STATUS] = 0x18,
+   [NAND_DEV0_CFG0] = 0x20,
+   [NAND_DEV0_CFG1] = 0x24,
+   [NAND_DEV0_ECC_CFG] =

[PATCH 12/14] qcom: mtd: nand: change register offset defines with enums

2017-06-29 Thread Abhishek Sahu 
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping array which contains controller register offsets for
each register offset enumeration. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.

Signed-off-by: Abhishek Sahu 
---
 drivers/mtd/nand/qcom_nandc.c | 136 +++---
 1 file changed, 89 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 6d749b6..24750e6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -24,43 +24,6 @@
 #include 
 #include 
 
-/* NANDc reg offsets */
-#defineNAND_FLASH_CMD  0x00
-#defineNAND_ADDR0  0x04
-#defineNAND_ADDR1  0x08
-#defineNAND_FLASH_CHIP_SELECT  0x0c
-#defineNAND_EXEC_CMD   0x10
-#defineNAND_FLASH_STATUS   0x14
-#defineNAND_BUFFER_STATUS  0x18
-#defineNAND_DEV0_CFG0  0x20
-#defineNAND_DEV0_CFG1  0x24
-#defineNAND_DEV0_ECC_CFG   0x28
-#defineNAND_DEV1_ECC_CFG   0x2c
-#defineNAND_DEV1_CFG0  0x30
-#defineNAND_DEV1_CFG1  0x34
-#defineNAND_READ_ID0x40
-#defineNAND_READ_STATUS0x44
-#defineNAND_DEV_CMD0   0xa0
-#defineNAND_DEV_CMD1   0xa4
-#defineNAND_DEV_CMD2   0xa8
-#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG   0xe0
-#defineNAND_ERASED_CW_DETECT_CFG   0xe8
-#defineNAND_ERASED_CW_DETECT_STATUS0xec
-#defineNAND_EBI2_ECC_BUF_CFG   0xf0
-#defineFLASH_BUF_ACC   0x100
-
-#defineNAND_CTRL   0xf00
-#defineNAND_VERSION0xf08
-#defineNAND_READ_LOCATION_00xf20
-#defineNAND_READ_LOCATION_10xf24
-#defineNAND_READ_LOCATION_20xf28
-#defineNAND_READ_LOCATION_30xf2c
-
-/* dummy register offsets, used by write_reg_dma */
-#defineNAND_DEV_CMD1_RESTORE   0xdead
-#defineNAND_DEV_CMD_VLD_RESTORE0xbeef
-
 /* NAND_FLASH_CMD bits */
 #definePAGE_ACCBIT(4)
 #defineLAST_PAGE   BIT(5)
@@ -204,6 +167,44 @@
 #define QPIC_PER_CW_MAX_CMD_SGL(32)
 #define QPIC_PER_CW_MAX_DATA_SGL   (8)
 
+/* NANDc reg offsets enumeration */
+enum {
+   NAND_FLASH_CMD,
+   NAND_ADDR0,
+   NAND_ADDR1,
+   NAND_FLASH_CHIP_SELECT,
+   NAND_EXEC_CMD,
+   NAND_FLASH_STATUS,
+   NAND_BUFFER_STATUS,
+   NAND_DEV0_CFG0,
+   NAND_DEV0_CFG1,
+   NAND_DEV0_ECC_CFG,
+   NAND_DEV1_ECC_CFG,
+   NAND_DEV1_CFG0,
+   NAND_DEV1_CFG1,
+   NAND_READ_ID,
+   NAND_READ_STATUS,
+   NAND_DEV_CMD0,
+   NAND_DEV_CMD1,
+   NAND_DEV_CMD2,
+   NAND_DEV_CMD_VLD,
+   SFLASHC_BURST_CFG,
+   NAND_ERASED_CW_DETECT_CFG,
+   NAND_ERASED_CW_DETECT_STATUS,
+   NAND_EBI2_ECC_BUF_CFG,
+   FLASH_BUF_ACC,
+   NAND_CTRL,
+   NAND_VERSION,
+   NAND_READ_LOCATION_0,
+   NAND_READ_LOCATION_1,
+   NAND_READ_LOCATION_2,
+   NAND_READ_LOCATION_3,
+
+   /* dummy register offsets, used by write_reg_dma */
+   NAND_DEV_CMD1_RESTORE,
+   NAND_DEV_CMD_VLD_RESTORE,
+};
+
 /*
  * This data type corresponds to the BAM transaction which will be used for all
  * NAND transfers.
@@ -326,6 +327,7 @@ struct nandc_regs {
  * bam dma
  * @max_cwperpage: maximum qpic codeword required. calcualted
  * from all nand device pagesize
+ * @regs_offsets:  register offset mapping array
  */
 struct qcom_nand_controller {
struct nand_hw_control controller;
@@ -371,6 +373,7 @@ struct qcom_nand_controller {
 
u32 cmd1, vld;
u32 ecc_modes;
+   const u32 *regs_offsets;
 };
 
 /*
@@ -434,6 +437,40 @@ struct qcom_nand_driver_data {
bool dma_bam_enabled;
 };
 
+/* Mapping table which contains the actual register offsets */
+static const u32 regs_offsets[] = {
+   [NAND_FLASH_CMD] = 0x00,
+   [NAND_ADDR0] = 0x04,
+   [NAND_ADDR1] = 0x08,
+   [NAND_FLASH_CHIP_SELECT] = 0x0c,
+   [NAND_EXEC_CMD] = 0x10,
+   [NAND_FLASH_STATUS] = 0x14,
+   [NAND_BUFFER_STATUS] = 0x18,
+   [NAND_DEV0_CFG0] = 0x20,
+   [NAND_DEV0_CFG1] = 0x24,
+   [NAND_DEV0_ECC_CFG] = 0x28,
+