[PATCH 2/2] ARM: sun7i: A20: Add display and TCON clocks

2016-05-10 Thread Priit Laes 
Enable the display and TCON clocks that are needed to drive the display
engine, tcon and TV encoders.

Signed-off-by: Priit Laes 
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 85 +---
 1 file changed, 80 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index febdf4c..82e28c3 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -67,8 +67,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
-   clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>, <_gates 26>;
+   clocks = <_gates 36>, <_gates 43>, <_gates 
44>,
+<_be0_clk>, <_ch0_clk>, <_gates 
26>;
status = "disabled";
};
 
@@ -76,7 +76,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>,
+   clocks = <_gates 36>, <_gates 44>,
+<_be0_clk>, <_ch0_clk>,
 <_gates 26>;
status = "disabled";
};
@@ -85,8 +86,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
-   clocks = < 1>,
-<_gates 34>, <_gates 36>, <_gates 
44>,
+   clocks = <_gates 34>, <_gates 36>, <_gates 
44>,
+<_be0_clk>, <_ch0_clk>,
 <_gates 5>, <_gates 26>;
status = "disabled";
};
@@ -580,6 +581,80 @@
 "dram_de_mp", "dram_ace";
};
 
+   de_be0_clk: clk@01c20104 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20104 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be0";
+   };
+
+   de_be1_clk: clk@01c20108 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20108 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be1";
+   };
+
+   de_fe0_clk: clk@01c2010c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c2010c 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe0";
+   };
+
+   de_fe1_clk: clk@01c20110 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20110 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe1";
+   };
+
+   tcon0_ch0_clk: clk@01c20118 {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c20118 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon0-ch0-sclk";
+
+   };
+
+   tcon1_ch0_clk: clk@01c2011c {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+   reg = <0x01c2011c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon1-ch0-sclk";
+
+   };
+
+   tcon0_ch1_clk: clk@01c2012c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c2012c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon0-ch1-sclk";
+
+   };
+
+   tcon1_ch1_clk: clk@01c20130 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+

[PATCH 2/2] ARM: sun7i: A20: Add display and TCON clocks

2016-05-10 Thread Priit Laes 
Enable the display and TCON clocks that are needed to drive the display
engine, tcon and TV encoders.

Signed-off-by: Priit Laes 
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 85 +---
 1 file changed, 80 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index febdf4c..82e28c3 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -67,8 +67,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
-   clocks = < 1>, <_gates 36>, <_gates 43>,
-<_gates 44>, <_gates 26>;
+   clocks = <_gates 36>, <_gates 43>, <_gates 
44>,
+<_be0_clk>, <_ch0_clk>, <_gates 
26>;
status = "disabled";
};
 
@@ -76,7 +76,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 1>, <_gates 36>, <_gates 44>,
+   clocks = <_gates 36>, <_gates 44>,
+<_be0_clk>, <_ch0_clk>,
 <_gates 26>;
status = "disabled";
};
@@ -85,8 +86,8 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
-   clocks = < 1>,
-<_gates 34>, <_gates 36>, <_gates 
44>,
+   clocks = <_gates 34>, <_gates 36>, <_gates 
44>,
+<_be0_clk>, <_ch0_clk>,
 <_gates 5>, <_gates 26>;
status = "disabled";
};
@@ -580,6 +581,80 @@
 "dram_de_mp", "dram_ace";
};
 
+   de_be0_clk: clk@01c20104 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20104 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be0";
+   };
+
+   de_be1_clk: clk@01c20108 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20108 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-be1";
+   };
+
+   de_fe0_clk: clk@01c2010c {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c2010c 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe0";
+   };
+
+   de_fe1_clk: clk@01c20110 {
+   #clock-cells = <0>;
+   #reset-cells = <0>;
+   compatible = "allwinner,sun4i-a10-display-clk";
+   reg = <0x01c20110 0x4>;
+   clocks = <>, <>, < 1>;
+   clock-output-names = "de-fe1";
+   };
+
+   tcon0_ch0_clk: clk@01c20118 {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c20118 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon0-ch0-sclk";
+
+   };
+
+   tcon1_ch0_clk: clk@01c2011c {
+   #clock-cells = <0>;
+   #reset-cells = <1>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+   reg = <0x01c2011c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon1-ch0-sclk";
+
+   };
+
+   tcon0_ch1_clk: clk@01c2012c {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+   reg = <0x01c2012c 0x4>;
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "tcon0-ch1-sclk";
+
+   };
+
+   tcon1_ch1_clk: clk@01c20130 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+   reg =