Re: [PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On 8/10/2018 7:58 PM, Jerome Brunet wrote:
> On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
>> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the serial console.
>>
>> Signed-off-by: Jianxin
>
> Could please fix your signoff here ? Your last name went missing
>
OK, I will fix this mistake. Thank you for your review.
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile| 1 +
>> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
>>
>> 3 files changed, 197 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
>> b/arch/arm64/boot/dts/amlogic/Makefile
>> index a97c0e2..c31f29d6 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -1,5 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
>> +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> new file mode 100644
>> index 000..d267a37
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> @@ -0,0 +1,22 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "meson-g12a.dtsi"
>> +
>> +/ {
>> +compatible = "amlogic,u200", "amlogic,g12a";
>> +model = "Amlogic Meson G12A U200 Development Board";
>> +
>> +aliases {
>> +serial0 = _AO;
>> +};
>> +};
>> +
>> +_AO {
>> +status = "okay";
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> new file mode 100644
>> index 000..64a0f2e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -0,0 +1,174 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +
>> +/ {
>
> Could you please order the subnodes alphabetically ?
>
> In general, we should try to order nodes by addresses when there is one and
> alphabetically when there is none. This is something we have to fix for the
> AXG
> as well.
>
>
OK, I will fix this in g12a first.>> + compatible = "amlogic,g12a";
>> +
>> +interrupt-parent = <>;
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
>
> It's the only one (for now at least) so it's not really an alternate, isn't
> it ?
>
Yes, the reserved memory for BL31 is a must. I will remove 'Alternate' in V2.
>> +secmon_reserved: secmon@500 {
>> +reg = <0x0 0x0500 0x0 0x30>;
>> +no-map;
>> +};
>> +};
>> +
>> +cpus {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x0>;
>> +
>> +cpu0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu1: cpu@1 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x1>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu2: cpu@2 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x2>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu3: cpu@3 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x3>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +l2: l2-cache0 {
>> +compatible = "cache";
>> +};
>> +};
>> +
>> +psci {
>> +compatible = "arm,psci-1.0";
Re: [PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On 8/10/2018 7:58 PM, Jerome Brunet wrote:
> On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
>> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
>> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
>> Timer, UART. It's capable of booting up into the serial console.
>>
>> Signed-off-by: Jianxin
>
> Could please fix your signoff here ? Your last name went missing
>
OK, I will fix this mistake. Thank you for your review.
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile| 1 +
>> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
>>
>> 3 files changed, 197 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
>> b/arch/arm64/boot/dts/amlogic/Makefile
>> index a97c0e2..c31f29d6 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -1,5 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
>> +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
>> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> new file mode 100644
>> index 000..d267a37
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
>> @@ -0,0 +1,22 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "meson-g12a.dtsi"
>> +
>> +/ {
>> +compatible = "amlogic,u200", "amlogic,g12a";
>> +model = "Amlogic Meson G12A U200 Development Board";
>> +
>> +aliases {
>> +serial0 = _AO;
>> +};
>> +};
>> +
>> +_AO {
>> +status = "okay";
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> new file mode 100644
>> index 000..64a0f2e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -0,0 +1,174 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +
>> +/ {
>
> Could you please order the subnodes alphabetically ?
>
> In general, we should try to order nodes by addresses when there is one and
> alphabetically when there is none. This is something we have to fix for the
> AXG
> as well.
>
>
OK, I will fix this in g12a first.>> + compatible = "amlogic,g12a";
>> +
>> +interrupt-parent = <>;
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +
>> +reserved-memory {
>> +#address-cells = <2>;
>> +#size-cells = <2>;
>> +ranges;
>> +
>> +/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
>
> It's the only one (for now at least) so it's not really an alternate, isn't
> it ?
>
Yes, the reserved memory for BL31 is a must. I will remove 'Alternate' in V2.
>> +secmon_reserved: secmon@500 {
>> +reg = <0x0 0x0500 0x0 0x30>;
>> +no-map;
>> +};
>> +};
>> +
>> +cpus {
>> +#address-cells = <0x2>;
>> +#size-cells = <0x0>;
>> +
>> +cpu0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu1: cpu@1 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x1>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu2: cpu@2 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x2>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +cpu3: cpu@3 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x3>;
>> +enable-method = "psci";
>> +next-level-cache = <>;
>> +};
>> +
>> +l2: l2-cache0 {
>> +compatible = "cache";
>> +};
>> +};
>> +
>> +psci {
>> +compatible = "arm,psci-1.0";
Re: [PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
> Timer, UART. It's capable of booting up into the serial console.
>
> Signed-off-by: Jianxin
Could please fix your signoff here ? Your last name went missing
> ---
> arch/arm64/boot/dts/amlogic/Makefile| 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
>
> 3 files changed, 197 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index a97c0e2..c31f29d6 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> new file mode 100644
> index 000..d267a37
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-g12a.dtsi"
> +
> +/ {
> + compatible = "amlogic,u200", "amlogic,g12a";
> + model = "Amlogic Meson G12A U200 Development Board";
> +
> + aliases {
> + serial0 = _AO;
> + };
> +};
> +
> +_AO {
> + status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> new file mode 100644
> index 000..64a0f2e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -0,0 +1,174 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
Could you please order the subnodes alphabetically ?
In general, we should try to order nodes by addresses when there is one and
alphabetically when there is none. This is something we have to fix for the AXG
as well.
> + compatible = "amlogic,g12a";
> +
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
It's the only one (for now at least) so it's not really an alternate, isn't it ?
> + secmon_reserved: secmon@500 {
> + reg = <0x0 0x0500 0x0 0x30>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> +
Re: [PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
> Timer, UART. It's capable of booting up into the serial console.
>
> Signed-off-by: Jianxin
Could please fix your signoff here ? Your last name went missing
> ---
> arch/arm64/boot/dts/amlogic/Makefile| 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
>
> 3 files changed, 197 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index a97c0e2..c31f29d6 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> new file mode 100644
> index 000..d267a37
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-g12a.dtsi"
> +
> +/ {
> + compatible = "amlogic,u200", "amlogic,g12a";
> + model = "Amlogic Meson G12A U200 Development Board";
> +
> + aliases {
> + serial0 = _AO;
> + };
> +};
> +
> +_AO {
> + status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> new file mode 100644
> index 000..64a0f2e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -0,0 +1,174 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
Could you please order the subnodes alphabetically ?
In general, we should try to order nodes by addresses when there is one and
alphabetically when there is none. This is something we have to fix for the AXG
as well.
> + compatible = "amlogic,g12a";
> +
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
It's the only one (for now at least) so it's not really an alternate, isn't it ?
> + secmon_reserved: secmon@500 {
> + reg = <0x0 0x0500 0x0 0x30>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> +
[PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin
---
arch/arm64/boot/dts/amlogic/Makefile| 1 +
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
3 files changed, 197 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index a97c0e2..c31f29d6 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
new file mode 100644
index 000..d267a37
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+
+/ {
+ compatible = "amlogic,u200", "amlogic,g12a";
+ model = "Amlogic Meson G12A U200 Development Board";
+
+ aliases {
+ serial0 = _AO;
+ };
+};
+
+_AO {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
new file mode 100644
index 000..64a0f2e
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "amlogic,g12a";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@500 {
+ reg = <0x0 0x0500 0x0 0x30>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb: apb@ffe0 {
+ compatible = "simple-bus";
+ reg = <0x0 0xffe0 0x0 0x20>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0
[PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
Timer, UART. It's capable of booting up into the serial console.
Signed-off-by: Jianxin
---
arch/arm64/boot/dts/amlogic/Makefile| 1 +
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
3 files changed, 197 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile
b/arch/arm64/boot/dts/amlogic/Makefile
index a97c0e2..c31f29d6 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
new file mode 100644
index 000..d267a37
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+
+/ {
+ compatible = "amlogic,u200", "amlogic,g12a";
+ model = "Amlogic Meson G12A U200 Development Board";
+
+ aliases {
+ serial0 = _AO;
+ };
+};
+
+_AO {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
new file mode 100644
index 000..64a0f2e
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#include
+#include
+#include
+
+/ {
+ compatible = "amlogic,g12a";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@500 {
+ reg = <0x0 0x0500 0x0 0x30>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ apb: apb@ffe0 {
+ compatible = "simple-bus";
+ reg = <0x0 0xffe0 0x0 0x20>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0
