RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-07 Thread Anson Huang 


Best Regards!
Anson Huang


> -Original Message-
> From: Rafael J. Wysocki [mailto:r...@rjwysocki.net]
> Sent: 2018-01-08 7:34 AM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: Rafael J. Wysocki <raf...@kernel.org>; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux PM  p...@vger.kernel.org>; Linux Kernel Mailing List  ker...@vger.kernel.org>; Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> Russell King - ARM Linux <li...@armlinux.org.uk>; Viresh Kumar
> <viresh.ku...@linaro.org>; Jacky Bai <ping....@nxp.com>; A.s. Dong
> <aisheng.d...@nxp.com>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> > Hi, Rafael
> >
> > Best Regards!
> > Anson Huang
> >
> >
> > > -Original Message-
> > > From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of
> > > Rafael J. Wysocki
> > > Sent: 2018-01-05 8:21 PM
> > > To: Anson Huang <anson.hu...@nxp.com>
> > > Cc: linux-arm-ker...@lists.infradead.org;
> > > devicet...@vger.kernel.org; Linux PM <linux...@vger.kernel.org>;
> > > Linux Kernel Mailing List ; Shawn Guo
> > > <shawn...@kernel.org>; Sascha Hauer <ker...@pengutronix.de>; Fabio
> > > Estevam <fabio.este...@nxp.com>; Rob Herring <robh...@kernel.org>;
> > > Mark Rutland <mark.rutl...@arm.com>; Russell King - ARM Linux
> > > <li...@armlinux.org.uk>; Rafael J. Wysocki <r...@rjwysocki.net>;
> > > Viresh Kumar <viresh.ku...@linaro.org>; Jacky Bai
> > > <ping@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>
> > > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point
> > > for i.mx6ul
> > >
> > > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <anson.hu...@nxp.com>
> wrote:
> > > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > > speed grading fuse set to 2b'10 supports 696MHz operating point,
> > > > so, speed grading check is also added for i.MX6UL in this patch,
> > > > the clock tree for each operating point are as below:
> > > >
> > > > 696MHz:
> > > > pll1   69600
> > > >pll1_bypass 69600
> > > >   pll1_sys 69600
> > > >  pll1_sw   69600
> > > > arm69600
> > > > 528MHz:
> > > > pll2   52800
> > > >pll2_bypass 52800
> > > >   pll2_bus 52800
> > > >  ca7_secondary_sel 52800
> > > > step   52800
> > > >pll1_sw 52800
> > > >   arm  52800
> > > > 396MHz:
> > > > pll2_pfd2_396m 39600
> > > >ca7_secondary_sel   39600
> > > >   step 39600
> > > >  pll1_sw   39600
> > > > arm39600
> > > > 198MHz:
> > > > pll2_pfd2_396m 39600
> > > >ca7_secondary_sel   39600
> > > >   step 39600
> > > >  pll1_sw   39600
> > > > arm19800
> > > >
> > > > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > >
> > > This doesn't apply for me and in a nontrivial way.
> > >
> > > What kernel is it against?
> >
> > I did it based on linux-next, it should be on linux-next-pm branch, I
> > redo the patch set V2 based on linux-next-pm, also redo the test,
> > sorry for the inconvenience.
> 
> But you didn't add the Reviewed-by: tags from Fabio to them.
> 
> Was that on purpose or by mistake?
> 
> Thanks,
> Rafael

It was my mistake, I thought it will be added by maintainer, I will add them 
and set a V3
patch set. Thanks.

Anson.

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-07 Thread Anson Huang 


Best Regards!
Anson Huang


> -Original Message-
> From: Rafael J. Wysocki [mailto:r...@rjwysocki.net]
> Sent: 2018-01-08 7:34 AM
> To: Anson Huang 
> Cc: Rafael J. Wysocki ; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux PM  p...@vger.kernel.org>; Linux Kernel Mailing List  ker...@vger.kernel.org>; Shawn Guo ; Sascha Hauer
> ; Fabio Estevam ; Rob
> Herring ; Mark Rutland ;
> Russell King - ARM Linux ; Viresh Kumar
> ; Jacky Bai ; A.s. Dong
> 
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> > Hi, Rafael
> >
> > Best Regards!
> > Anson Huang
> >
> >
> > > -Original Message-
> > > From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of
> > > Rafael J. Wysocki
> > > Sent: 2018-01-05 8:21 PM
> > > To: Anson Huang 
> > > Cc: linux-arm-ker...@lists.infradead.org;
> > > devicet...@vger.kernel.org; Linux PM ;
> > > Linux Kernel Mailing List ; Shawn Guo
> > > ; Sascha Hauer ; Fabio
> > > Estevam ; Rob Herring ;
> > > Mark Rutland ; Russell King - ARM Linux
> > > ; Rafael J. Wysocki ;
> > > Viresh Kumar ; Jacky Bai
> > > ; A.s. Dong 
> > > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point
> > > for i.mx6ul
> > >
> > > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang 
> wrote:
> > > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > > speed grading fuse set to 2b'10 supports 696MHz operating point,
> > > > so, speed grading check is also added for i.MX6UL in this patch,
> > > > the clock tree for each operating point are as below:
> > > >
> > > > 696MHz:
> > > > pll1   69600
> > > >pll1_bypass 69600
> > > >   pll1_sys 69600
> > > >  pll1_sw   69600
> > > > arm69600
> > > > 528MHz:
> > > > pll2   52800
> > > >pll2_bypass 52800
> > > >   pll2_bus 52800
> > > >  ca7_secondary_sel 52800
> > > > step   52800
> > > >pll1_sw 52800
> > > >   arm  52800
> > > > 396MHz:
> > > > pll2_pfd2_396m 39600
> > > >ca7_secondary_sel   39600
> > > >   step 39600
> > > >  pll1_sw   39600
> > > > arm39600
> > > > 198MHz:
> > > > pll2_pfd2_396m 39600
> > > >ca7_secondary_sel   39600
> > > >   step 39600
> > > >  pll1_sw   39600
> > > > arm19800
> > > >
> > > > Signed-off-by: Anson Huang 
> > >
> > > This doesn't apply for me and in a nontrivial way.
> > >
> > > What kernel is it against?
> >
> > I did it based on linux-next, it should be on linux-next-pm branch, I
> > redo the patch set V2 based on linux-next-pm, also redo the test,
> > sorry for the inconvenience.
> 
> But you didn't add the Reviewed-by: tags from Fabio to them.
> 
> Was that on purpose or by mistake?
> 
> Thanks,
> Rafael

It was my mistake, I thought it will be added by maintainer, I will add them 
and set a V3
patch set. Thanks.

Anson.

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-07 Thread Rafael J. Wysocki 
On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> Hi, Rafael
> 
> Best Regards!
> Anson Huang
> 
> 
> > -Original Message-
> > From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of Rafael
> > J. Wysocki
> > Sent: 2018-01-05 8:21 PM
> > To: Anson Huang <anson.hu...@nxp.com>
> > Cc: linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux
> > PM <linux...@vger.kernel.org>; Linux Kernel Mailing List  > ker...@vger.kernel.org>; Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> > <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> > Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> > Russell King - ARM Linux <li...@armlinux.org.uk>; Rafael J. Wysocki
> > <r...@rjwysocki.net>; Viresh Kumar <viresh.ku...@linaro.org>; Jacky Bai
> > <ping@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>
> > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> > i.mx6ul
> > 
> > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <anson.hu...@nxp.com> wrote:
> > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > > speed grading check is also added for i.MX6UL in this patch, the clock
> > > tree for each operating point are as below:
> > >
> > > 696MHz:
> > > pll1   69600
> > >pll1_bypass 69600
> > >   pll1_sys 69600
> > >  pll1_sw   69600
> > > arm69600
> > > 528MHz:
> > > pll2   52800
> > >pll2_bypass 52800
> > >   pll2_bus 52800
> > >  ca7_secondary_sel 52800
> > > step   52800
> > >pll1_sw 52800
> > >   arm  52800
> > > 396MHz:
> > > pll2_pfd2_396m 39600
> > >ca7_secondary_sel   39600
> > >   step 39600
> > >  pll1_sw   39600
> > > arm39600
> > > 198MHz:
> > > pll2_pfd2_396m 39600
> > >ca7_secondary_sel   39600
> > >   step 39600
> > >  pll1_sw   39600
> > > arm19800
> > >
> > > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > 
> > This doesn't apply for me and in a nontrivial way.
> > 
> > What kernel is it against?
> 
> I did it based on linux-next, it should be on linux-next-pm branch, I redo
> the patch set V2 based on linux-next-pm, also redo the test,
> sorry for the inconvenience.

But you didn't add the Reviewed-by: tags from Fabio to them.

Was that on purpose or by mistake?

Thanks,
Rafael

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-07 Thread Rafael J. Wysocki 
On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> Hi, Rafael
> 
> Best Regards!
> Anson Huang
> 
> 
> > -Original Message-
> > From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of Rafael
> > J. Wysocki
> > Sent: 2018-01-05 8:21 PM
> > To: Anson Huang 
> > Cc: linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux
> > PM ; Linux Kernel Mailing List  > ker...@vger.kernel.org>; Shawn Guo ; Sascha Hauer
> > ; Fabio Estevam ; Rob
> > Herring ; Mark Rutland ;
> > Russell King - ARM Linux ; Rafael J. Wysocki
> > ; Viresh Kumar ; Jacky Bai
> > ; A.s. Dong 
> > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> > i.mx6ul
> > 
> > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang  wrote:
> > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > > speed grading check is also added for i.MX6UL in this patch, the clock
> > > tree for each operating point are as below:
> > >
> > > 696MHz:
> > > pll1   69600
> > >pll1_bypass 69600
> > >   pll1_sys 69600
> > >  pll1_sw   69600
> > > arm69600
> > > 528MHz:
> > > pll2   52800
> > >pll2_bypass 52800
> > >   pll2_bus 52800
> > >  ca7_secondary_sel 52800
> > > step   52800
> > >pll1_sw 52800
> > >   arm  52800
> > > 396MHz:
> > > pll2_pfd2_396m 39600
> > >ca7_secondary_sel   39600
> > >   step 39600
> > >  pll1_sw   39600
> > > arm39600
> > > 198MHz:
> > > pll2_pfd2_396m 39600
> > >ca7_secondary_sel   39600
> > >   step 39600
> > >  pll1_sw   39600
> > > arm19800
> > >
> > > Signed-off-by: Anson Huang 
> > 
> > This doesn't apply for me and in a nontrivial way.
> > 
> > What kernel is it against?
> 
> I did it based on linux-next, it should be on linux-next-pm branch, I redo
> the patch set V2 based on linux-next-pm, also redo the test,
> sorry for the inconvenience.

But you didn't add the Reviewed-by: tags from Fabio to them.

Was that on purpose or by mistake?

Thanks,
Rafael

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-05 Thread Anson Huang 
Hi, Rafael

Best Regards!
Anson Huang


> -Original Message-
> From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of Rafael
> J. Wysocki
> Sent: 2018-01-05 8:21 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux
> PM <linux...@vger.kernel.org>; Linux Kernel Mailing List  ker...@vger.kernel.org>; Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> Russell King - ARM Linux <li...@armlinux.org.uk>; Rafael J. Wysocki
> <r...@rjwysocki.net>; Viresh Kumar <viresh.ku...@linaro.org>; Jacky Bai
> <ping@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <anson.hu...@nxp.com> wrote:
> > Add 696MHz operating point for i.MX6UL, only for those parts with
> > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > speed grading check is also added for i.MX6UL in this patch, the clock
> > tree for each operating point are as below:
> >
> > 696MHz:
> > pll1   69600
> >pll1_bypass 69600
> >   pll1_sys 69600
> >  pll1_sw   69600
> > arm69600
> > 528MHz:
> > pll2   52800
> >pll2_bypass 52800
> >   pll2_bus 52800
> >  ca7_secondary_sel 52800
> > step   52800
> >pll1_sw 52800
> >   arm  52800
> > 396MHz:
> > pll2_pfd2_396m 39600
> >ca7_secondary_sel   39600
> >   step 39600
> >  pll1_sw   39600
> > arm39600
> > 198MHz:
> > pll2_pfd2_396m 39600
> >ca7_secondary_sel   39600
> >   step 39600
> >  pll1_sw   39600
> > arm19800
> >
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> 
> This doesn't apply for me and in a nontrivial way.
> 
> What kernel is it against?

I did it based on linux-next, it should be on linux-next-pm branch, I redo
the patch set V2 based on linux-next-pm, also redo the test,
sorry for the inconvenience.

Anson.

> 
> > ---
> >  drivers/cpufreq/imx6q-cpufreq.c | 46
> > -
> >  1 file changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index d9b2c2d..cbda0cc 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> > clk_set_parent(secondary_sel_clk, 
> > pll2_pfd2_396m_clk);
> > clk_set_parent(step_clk, secondary_sel_clk);
> > clk_set_parent(pll1_sw_clk, step_clk);
> > +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> > +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> > +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > +   }
> > } else {
> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> > clk_set_parent(pll1_sw_clk, step_clk); @@ -244,6
> > +248,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
> > of_node_put(np);
> >  }
> >
> > +#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
> > +
> > +static void imx6ul_opp_check_speed_grading(struct device *dev) {
> > +   struct device_node *np;
> > +   void __iomem *base;
> > +   u32 val;
> > +
> > +   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> > +   if (!np)
> > +   return;
> > +
> > +   base = of_iomap(np, 0);
> > +   if (!base) {
> > +   dev_err(dev, "failed to map ocotp\n");
> > +   goto put_node;
> > +   }
> > +
> > +   /*
> > +* Speed GRADING[1:0] defines the max speed of ARM:
> > +

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-05 Thread Anson Huang 
Hi, Rafael

Best Regards!
Anson Huang


> -Original Message-
> From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of Rafael
> J. Wysocki
> Sent: 2018-01-05 8:21 PM
> To: Anson Huang 
> Cc: linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux
> PM ; Linux Kernel Mailing List  ker...@vger.kernel.org>; Shawn Guo ; Sascha Hauer
> ; Fabio Estevam ; Rob
> Herring ; Mark Rutland ;
> Russell King - ARM Linux ; Rafael J. Wysocki
> ; Viresh Kumar ; Jacky Bai
> ; A.s. Dong 
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang  wrote:
> > Add 696MHz operating point for i.MX6UL, only for those parts with
> > speed grading fuse set to 2b'10 supports 696MHz operating point, so,
> > speed grading check is also added for i.MX6UL in this patch, the clock
> > tree for each operating point are as below:
> >
> > 696MHz:
> > pll1   69600
> >pll1_bypass 69600
> >   pll1_sys 69600
> >  pll1_sw   69600
> > arm69600
> > 528MHz:
> > pll2   52800
> >pll2_bypass 52800
> >   pll2_bus 52800
> >  ca7_secondary_sel 52800
> > step   52800
> >pll1_sw 52800
> >   arm  52800
> > 396MHz:
> > pll2_pfd2_396m 39600
> >ca7_secondary_sel   39600
> >   step 39600
> >  pll1_sw   39600
> > arm39600
> > 198MHz:
> > pll2_pfd2_396m 39600
> >ca7_secondary_sel   39600
> >   step 39600
> >  pll1_sw   39600
> > arm19800
> >
> > Signed-off-by: Anson Huang 
> 
> This doesn't apply for me and in a nontrivial way.
> 
> What kernel is it against?

I did it based on linux-next, it should be on linux-next-pm branch, I redo
the patch set V2 based on linux-next-pm, also redo the test,
sorry for the inconvenience.

Anson.

> 
> > ---
> >  drivers/cpufreq/imx6q-cpufreq.c | 46
> > -
> >  1 file changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index d9b2c2d..cbda0cc 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> > clk_set_parent(secondary_sel_clk, 
> > pll2_pfd2_396m_clk);
> > clk_set_parent(step_clk, secondary_sel_clk);
> > clk_set_parent(pll1_sw_clk, step_clk);
> > +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> > +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> > +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > +   }
> > } else {
> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> > clk_set_parent(pll1_sw_clk, step_clk); @@ -244,6
> > +248,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
> > of_node_put(np);
> >  }
> >
> > +#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
> > +
> > +static void imx6ul_opp_check_speed_grading(struct device *dev) {
> > +   struct device_node *np;
> > +   void __iomem *base;
> > +   u32 val;
> > +
> > +   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> > +   if (!np)
> > +   return;
> > +
> > +   base = of_iomap(np, 0);
> > +   if (!base) {
> > +   dev_err(dev, "failed to map ocotp\n");
> > +   goto put_node;
> > +   }
> > +
> > +   /*
> > +* Speed GRADING[1:0] defines the max speed of ARM:
> > +* 2b'00: Reserved;
> > +* 2b'01: 52800Hz;
> > +* 2b'10: 69600Hz;
> > +* 2b'11: Reserved;
> > +* We need to set the max speed of ARM according to fuse map.
> > +*/
> > +   val = readl_relaxed(base + OCOTP_CFG3);
> > +   val >>= OCOTP_CFG3_SPEED_SHIFT;
> > +   val &= 0x

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-05 Thread Rafael J. Wysocki 
On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang  wrote:
> Add 696MHz operating point for i.MX6UL, only for those
> parts with speed grading fuse set to 2b'10 supports
> 696MHz operating point, so, speed grading check is also
> added for i.MX6UL in this patch, the clock tree for each
> operating point are as below:
>
> 696MHz:
> pll1   69600
>pll1_bypass 69600
>   pll1_sys 69600
>  pll1_sw   69600
> arm69600
> 528MHz:
> pll2   52800
>pll2_bypass 52800
>   pll2_bus 52800
>  ca7_secondary_sel 52800
> step   52800
>pll1_sw 52800
>   arm  52800
> 396MHz:
> pll2_pfd2_396m 39600
>ca7_secondary_sel   39600
>   step 39600
>  pll1_sw   39600
> arm39600
> 198MHz:
> pll2_pfd2_396m 39600
>ca7_secondary_sel   39600
>   step 39600
>  pll1_sw   39600
> arm19800
>
> Signed-off-by: Anson Huang 

This doesn't apply for me and in a nontrivial way.

What kernel is it against?

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 46 
> -
>  1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy 
> *policy, unsigned int index)
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +   }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> @@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device 
> *dev)
> of_node_put(np);
>  }
>
> +#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
> +
> +static void imx6ul_opp_check_speed_grading(struct device *dev)
> +{
> +   struct device_node *np;
> +   void __iomem *base;
> +   u32 val;
> +
> +   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> +   if (!np)
> +   return;
> +
> +   base = of_iomap(np, 0);
> +   if (!base) {
> +   dev_err(dev, "failed to map ocotp\n");
> +   goto put_node;
> +   }
> +
> +   /*
> +* Speed GRADING[1:0] defines the max speed of ARM:
> +* 2b'00: Reserved;
> +* 2b'01: 52800Hz;
> +* 2b'10: 69600Hz;
> +* 2b'11: Reserved;
> +* We need to set the max speed of ARM according to fuse map.
> +*/
> +   val = readl_relaxed(base + OCOTP_CFG3);
> +   val >>= OCOTP_CFG3_SPEED_SHIFT;
> +   val &= 0x3;
> +   if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
> +   if (dev_pm_opp_disable(dev, 69600))
> +   dev_warn(dev, "failed to disable 696MHz OPP\n");
> +   iounmap(base);
> +put_node:
> +   of_node_put(np);
> +}
> +
>  static int imx6q_cpufreq_probe(struct platform_device *pdev)
>  {
> struct device_node *np;
> @@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device 
> *pdev)
> goto put_reg;
> }
>
> -   imx6q_opp_check_speed_grading(cpu_dev);
> +   if (of_machine_is_compatible("fsl,imx6ul"))
> +   imx6ul_opp_check_speed_grading(cpu_dev);
> +   else
> +   imx6q_opp_check_speed_grading(cpu_dev);
>
> /* Because we have added the OPPs here, we must free them */
> free_opp = true;
> --
> 1.9.1
>

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-05 Thread Rafael J. Wysocki 
On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang  wrote:
> Add 696MHz operating point for i.MX6UL, only for those
> parts with speed grading fuse set to 2b'10 supports
> 696MHz operating point, so, speed grading check is also
> added for i.MX6UL in this patch, the clock tree for each
> operating point are as below:
>
> 696MHz:
> pll1   69600
>pll1_bypass 69600
>   pll1_sys 69600
>  pll1_sw   69600
> arm69600
> 528MHz:
> pll2   52800
>pll2_bypass 52800
>   pll2_bus 52800
>  ca7_secondary_sel 52800
> step   52800
>pll1_sw 52800
>   arm  52800
> 396MHz:
> pll2_pfd2_396m 39600
>ca7_secondary_sel   39600
>   step 39600
>  pll1_sw   39600
> arm39600
> 198MHz:
> pll2_pfd2_396m 39600
>ca7_secondary_sel   39600
>   step 39600
>  pll1_sw   39600
> arm19800
>
> Signed-off-by: Anson Huang 

This doesn't apply for me and in a nontrivial way.

What kernel is it against?

> ---
>  drivers/cpufreq/imx6q-cpufreq.c | 46 
> -
>  1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy 
> *policy, unsigned int index)
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +   }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> @@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device 
> *dev)
> of_node_put(np);
>  }
>
> +#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
> +
> +static void imx6ul_opp_check_speed_grading(struct device *dev)
> +{
> +   struct device_node *np;
> +   void __iomem *base;
> +   u32 val;
> +
> +   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
> +   if (!np)
> +   return;
> +
> +   base = of_iomap(np, 0);
> +   if (!base) {
> +   dev_err(dev, "failed to map ocotp\n");
> +   goto put_node;
> +   }
> +
> +   /*
> +* Speed GRADING[1:0] defines the max speed of ARM:
> +* 2b'00: Reserved;
> +* 2b'01: 52800Hz;
> +* 2b'10: 69600Hz;
> +* 2b'11: Reserved;
> +* We need to set the max speed of ARM according to fuse map.
> +*/
> +   val = readl_relaxed(base + OCOTP_CFG3);
> +   val >>= OCOTP_CFG3_SPEED_SHIFT;
> +   val &= 0x3;
> +   if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
> +   if (dev_pm_opp_disable(dev, 69600))
> +   dev_warn(dev, "failed to disable 696MHz OPP\n");
> +   iounmap(base);
> +put_node:
> +   of_node_put(np);
> +}
> +
>  static int imx6q_cpufreq_probe(struct platform_device *pdev)
>  {
> struct device_node *np;
> @@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device 
> *pdev)
> goto put_reg;
> }
>
> -   imx6q_opp_check_speed_grading(cpu_dev);
> +   if (of_machine_is_compatible("fsl,imx6ul"))
> +   imx6ul_opp_check_speed_grading(cpu_dev);
> +   else
> +   imx6q_opp_check_speed_grading(cpu_dev);
>
> /* Because we have added the OPPs here, we must free them */
> free_opp = true;
> --
> 1.9.1
>

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Anson Huang 
Post the discussion mail to arm kernel mail list, since last mail is rejected 
due to incorrect format, sorry for the confusion.

Best Regards!
Anson Huang


> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2018-01-02 11:33 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE  arm-ker...@lists.infradead.org>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS <devicet...@vger.kernel.org>; linux-
> p...@vger.kernel.org; linux-kernel <linux-kernel@vger.kernel.org>; Mark
> Rutland <mark.rutl...@arm.com>; A.s. Dong <aisheng.d...@nxp.com>; Jacky
> Bai <ping@nxp.com>; viresh kumar <viresh.ku...@linaro.org>;
> r...@rjwysocki.net; Russell King - ARM Linux <li...@armlinux.org.uk>; Rob
> Herring <robh...@kernel.org>; Sascha Hauer <ker...@pengutronix.de>;
> Fabio Estevam <fabio.este...@nxp.com>; Shawn Guo
> <shawn...@kernel.org>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang <anson.hu...@nxp.com> wrote:
> 
> > This change is only valid for mx6ul and mx6ull, other SoCs like
> > 6q/dl/qp are NOT impacted.
> 
> Thanks for the clarification:
> 
> Reviewed-by: Fabio Estevam <fabio.este...@nxp.com>

RE: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Anson Huang 
Post the discussion mail to arm kernel mail list, since last mail is rejected 
due to incorrect format, sorry for the confusion.

Best Regards!
Anson Huang


> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: 2018-01-02 11:33 PM
> To: Anson Huang 
> Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE  arm-ker...@lists.infradead.org>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS ; linux-
> p...@vger.kernel.org; linux-kernel ; Mark
> Rutland ; A.s. Dong ; Jacky
> Bai ; viresh kumar ;
> r...@rjwysocki.net; Russell King - ARM Linux ; Rob
> Herring ; Sascha Hauer ;
> Fabio Estevam ; Shawn Guo
> 
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
> 
> On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang  wrote:
> 
> > This change is only valid for mx6ul and mx6ull, other SoCs like
> > 6q/dl/qp are NOT impacted.
> 
> Thanks for the clarification:
> 
> Reviewed-by: Fabio Estevam

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang  wrote:

> This change is only valid for mx6ul and mx6ull, other SoCs like 6q/dl/qp are
> NOT impacted.

Thanks for the clarification:

Reviewed-by: Fabio Estevam

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang  wrote:

> This change is only valid for mx6ul and mx6ull, other SoCs like 6q/dl/qp are
> NOT impacted.

Thanks for the clarification:

Reviewed-by: Fabio Estevam

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
Hi Anson,

On Tue, Jan 2, 2018 at 1:05 PM, Anson Huang  wrote:

> This change is to support 696MHz operating point, both the speed grading
> check and pll rate change are necessary for 696MHz support, do you think
> they should be in different patch?

I thought  this could also change the behaviour for mx6q/dl/qp.

Are the others SoCs safe with this change?

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
Hi Anson,

On Tue, Jan 2, 2018 at 1:05 PM, Anson Huang  wrote:

> This change is to support 696MHz operating point, both the speed grading
> check and pll rate change are necessary for 696MHz support, do you think
> they should be in different patch?

I thought  this could also change the behaviour for mx6q/dl/qp.

Are the others SoCs safe with this change?

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang  wrote:

> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy 
> *policy, unsigned int index)
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +   }

This change should be part of a different patch.

Thanks

Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Fabio Estevam 
Hi Anson,

On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang  wrote:

> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index d9b2c2d..cbda0cc 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy 
> *policy, unsigned int index)
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> +   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
> +   clk_set_rate(pll1_sys_clk, new_freq * 1000);
> +   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> +   }

This change should be part of a different patch.

Thanks

[PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Anson Huang 
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:

696MHz:
pll1   69600
   pll1_bypass 69600
  pll1_sys 69600
 pll1_sw   69600
arm69600
528MHz:
pll2   52800
   pll2_bypass 52800
  pll2_bus 52800
 ca7_secondary_sel 52800
step   52800
   pll1_sw 52800
  arm  52800
396MHz:
pll2_pfd2_396m 39600
   ca7_secondary_sel   39600
  step 39600
 pll1_sw   39600
arm39600
198MHz:
pll2_pfd2_396m 39600
   ca7_secondary_sel   39600
  step 39600
 pll1_sw   39600
arm19800

Signed-off-by: Anson Huang 
---
 drivers/cpufreq/imx6q-cpufreq.c | 46 -
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index d9b2c2d..cbda0cc 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, 
unsigned int index)
clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
clk_set_parent(step_clk, secondary_sel_clk);
clk_set_parent(pll1_sw_clk, step_clk);
+   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
+   clk_set_rate(pll1_sys_clk, new_freq * 1000);
+   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+   }
} else {
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
@@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device 
*dev)
of_node_put(np);
 }
 
+#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
+
+static void imx6ul_opp_check_speed_grading(struct device *dev)
+{
+   struct device_node *np;
+   void __iomem *base;
+   u32 val;
+
+   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+   if (!np)
+   return;
+
+   base = of_iomap(np, 0);
+   if (!base) {
+   dev_err(dev, "failed to map ocotp\n");
+   goto put_node;
+   }
+
+   /*
+* Speed GRADING[1:0] defines the max speed of ARM:
+* 2b'00: Reserved;
+* 2b'01: 52800Hz;
+* 2b'10: 69600Hz;
+* 2b'11: Reserved;
+* We need to set the max speed of ARM according to fuse map.
+*/
+   val = readl_relaxed(base + OCOTP_CFG3);
+   val >>= OCOTP_CFG3_SPEED_SHIFT;
+   val &= 0x3;
+   if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+   if (dev_pm_opp_disable(dev, 69600))
+   dev_warn(dev, "failed to disable 696MHz OPP\n");
+   iounmap(base);
+put_node:
+   of_node_put(np);
+}
+
 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 {
struct device_node *np;
@@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device 
*pdev)
goto put_reg;
}
 
-   imx6q_opp_check_speed_grading(cpu_dev);
+   if (of_machine_is_compatible("fsl,imx6ul"))
+   imx6ul_opp_check_speed_grading(cpu_dev);
+   else
+   imx6q_opp_check_speed_grading(cpu_dev);
 
/* Because we have added the OPPs here, we must free them */
free_opp = true;
-- 
1.9.1

[PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul

2018-01-02 Thread Anson Huang 
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:

696MHz:
pll1   69600
   pll1_bypass 69600
  pll1_sys 69600
 pll1_sw   69600
arm69600
528MHz:
pll2   52800
   pll2_bypass 52800
  pll2_bus 52800
 ca7_secondary_sel 52800
step   52800
   pll1_sw 52800
  arm  52800
396MHz:
pll2_pfd2_396m 39600
   ca7_secondary_sel   39600
  step 39600
 pll1_sw   39600
arm39600
198MHz:
pll2_pfd2_396m 39600
   ca7_secondary_sel   39600
  step 39600
 pll1_sw   39600
arm19800

Signed-off-by: Anson Huang 
---
 drivers/cpufreq/imx6q-cpufreq.c | 46 -
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index d9b2c2d..cbda0cc 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -120,6 +120,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, 
unsigned int index)
clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
clk_set_parent(step_clk, secondary_sel_clk);
clk_set_parent(pll1_sw_clk, step_clk);
+   if (freq_hz > clk_get_rate(pll2_bus_clk)) {
+   clk_set_rate(pll1_sys_clk, new_freq * 1000);
+   clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+   }
} else {
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
@@ -244,6 +248,43 @@ static void imx6q_opp_check_speed_grading(struct device 
*dev)
of_node_put(np);
 }
 
+#define OCOTP_CFG3_6UL_SPEED_696MHZ0x2
+
+static void imx6ul_opp_check_speed_grading(struct device *dev)
+{
+   struct device_node *np;
+   void __iomem *base;
+   u32 val;
+
+   np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+   if (!np)
+   return;
+
+   base = of_iomap(np, 0);
+   if (!base) {
+   dev_err(dev, "failed to map ocotp\n");
+   goto put_node;
+   }
+
+   /*
+* Speed GRADING[1:0] defines the max speed of ARM:
+* 2b'00: Reserved;
+* 2b'01: 52800Hz;
+* 2b'10: 69600Hz;
+* 2b'11: Reserved;
+* We need to set the max speed of ARM according to fuse map.
+*/
+   val = readl_relaxed(base + OCOTP_CFG3);
+   val >>= OCOTP_CFG3_SPEED_SHIFT;
+   val &= 0x3;
+   if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+   if (dev_pm_opp_disable(dev, 69600))
+   dev_warn(dev, "failed to disable 696MHz OPP\n");
+   iounmap(base);
+put_node:
+   of_node_put(np);
+}
+
 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 {
struct device_node *np;
@@ -311,7 +352,10 @@ static int imx6q_cpufreq_probe(struct platform_device 
*pdev)
goto put_reg;
}
 
-   imx6q_opp_check_speed_grading(cpu_dev);
+   if (of_machine_is_compatible("fsl,imx6ul"))
+   imx6ul_opp_check_speed_grading(cpu_dev);
+   else
+   imx6q_opp_check_speed_grading(cpu_dev);
 
/* Because we have added the OPPs here, we must free them */
free_opp = true;
-- 
1.9.1