Re: [PATCH 2/4] dt-bindings: add bindings for rk3399 clock controller

[Rob Herring]

On Tue, Feb 23, 2016 at 03:01:02PM +0800, jianqun.xu wrote:
> From: Xing Zheng 
> 
> Add devicetree bindings for Rockchip cru which found on
> Rockchip SoCs.
> 
> Signed-off-by: Xing Zheng 
> Signed-off-by: Jianqun Xu 
> ---
>  .../bindings/clock/rockchip,rk3399-cru.txt | 82 
> ++
>  1 file changed, 82 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt


Acked-by: Rob Herring 

Re: [PATCH 2/4] dt-bindings: add bindings for rk3399 clock controller

[Rob Herring]

On Tue, Feb 23, 2016 at 03:01:02PM +0800, jianqun.xu wrote:
> From: Xing Zheng 
> 
> Add devicetree bindings for Rockchip cru which found on
> Rockchip SoCs.
> 
> Signed-off-by: Xing Zheng 
> Signed-off-by: Jianqun Xu 
> ---
>  .../bindings/clock/rockchip,rk3399-cru.txt | 82 
> ++
>  1 file changed, 82 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt


Acked-by: Rob Herring 

[PATCH 2/4] dt-bindings: add bindings for rk3399 clock controller

[jianqun.xu]

From: Xing Zheng 

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Xing Zheng 
Signed-off-by: Jianqun Xu 
---
 .../bindings/clock/rockchip,rk3399-cru.txt | 82 ++
 1 file changed, 82 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 000..07bcc6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,82 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional,
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: General Register Files
+
+   pmugrf: syscon@ff32 {
+   compatible = "rockchip,rk3399-pmugrf", "syscon";
+   reg = <0x0 0xff32 0x0 0x1000>;
+   };
+
+   grf: syscon@ff77 {
+   compatible = "rockchip,rk3399-grf", "syscon";
+   reg = <0x0 0xff77 0x0 0x1>;
+   };
+
+Example: Clock controller node:
+
+   pmucru: pmu-clock-controller@ff75 {
+   compatible = "rockchip,rk3399-pmucru";
+   reg = <0x0 0xff75 0x0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   cru: clock-controller@ff76 {
+   compatible = "rockchip,rk3399-cru";
+   reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@ff1a {
+   compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+   reg = <0x0 0xff18 0x0 0x100>;
+   clocks = < SCLK_UART0>, < PCLK_UART0>;
+   clock-names = "baudclk", "apb_pclk";
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   };
-- 
1.9.1

[PATCH 2/4] dt-bindings: add bindings for rk3399 clock controller

[jianqun.xu]

From: Xing Zheng 

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Xing Zheng 
Signed-off-by: Jianqun Xu 
---
 .../bindings/clock/rockchip,rk3399-cru.txt | 82 ++
 1 file changed, 82 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 000..07bcc6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,82 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional,
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: General Register Files
+
+   pmugrf: syscon@ff32 {
+   compatible = "rockchip,rk3399-pmugrf", "syscon";
+   reg = <0x0 0xff32 0x0 0x1000>;
+   };
+
+   grf: syscon@ff77 {
+   compatible = "rockchip,rk3399-grf", "syscon";
+   reg = <0x0 0xff77 0x0 0x1>;
+   };
+
+Example: Clock controller node:
+
+   pmucru: pmu-clock-controller@ff75 {
+   compatible = "rockchip,rk3399-pmucru";
+   reg = <0x0 0xff75 0x0 0x1000>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   cru: clock-controller@ff76 {
+   compatible = "rockchip,rk3399-cru";
+   reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+   uart0: serial@ff1a {
+   compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+   reg = <0x0 0xff18 0x0 0x100>;
+   clocks = < SCLK_UART0>, < PCLK_UART0>;
+   clock-names = "baudclk", "apb_pclk";
+   interrupts = ;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   };
-- 
1.9.1