Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-08 Thread hl 



On Monday, May 07, 2018 09:59 PM, Enric Balletbo Serra wrote:

Hi Lin,

Thanks for the patch, apart from the new build warnings introduced
some more comments below.

2018-05-04 10:08 GMT+02:00 Lin Huang :

the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
  drivers/phy/rockchip/phy-rockchip-typec.c | 286 +++---
  include/soc/rockchip/rockchip_phy_typec.h |  72 
  2 files changed, 259 insertions(+), 99 deletions(-)
  create mode 100644 include/soc/rockchip/rockchip_phy_typec.h

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 76a4b58..831a93b 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -63,6 +63,7 @@

  #include 
  #include 
+#include 

  #define CMN_SSM_BANDGAP(0x21 << 2)
  #define CMN_SSM_BIAS   (0x22 << 2)
@@ -323,23 +324,31 @@
   * clock 0: PLL 0 div 1
   * clock 1: PLL 1 div 2
   */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
  #define CLK_PLL_MASK   0x33

  #define CMN_READY  BIT(0)

+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
  #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
  #define DP_PLL_ENABLE  BIT(0)
  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00

-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)

-#define PHY_MODE_SET_TIMEOUT   10
+#define PHY_MODE_SET_TIMEOUT   100


Why do you need to increase this timeout? Is because the software link
training timed out using the old value?

That for debug, will fix it in next version.




  #define PIN_ASSIGN_C_E 0x51d9
  #define PIN_ASSIGN_D_F 0x5100
@@ -349,51 +358,7 @@
  #define MODE_DFP_USB   BIT(1)
  #define MODE_DFP_DPBIT(2)

-struct usb3phy_reg {
-   u32 offset;
-   u32 enable_bit;
-   u32 write_enable;
-};
-
-/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
- * @reg: the base address for usb3-phy config.
- * @typec_conn_dir: the register of type-c connector direction.
- * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
- * @external_psm: the register of type-c phy external psm clock.
- * @pipe_status: the register of type-c phy pipe status.
- * @usb3_host_disable: the register of type-c usb3 host disable.
- * @usb3_host_port: the register of type-c usb3 host port.
- * @uphy_dp_sel: the register of type-c phy DP select control.
- */
-struct rockchip_usb3phy_port_cfg {
-   unsigned int reg;
-   struct usb3phy_reg typec_conn_dir;
-   struct usb3phy_reg usb3tousb2_en;
-   struct usb3phy_reg external_psm;
-   struct usb3phy_reg pipe_status;
-   struct usb3phy_reg usb3_host_disable;
-   struct usb3phy_reg usb3_host_port;
-   struct usb3phy_reg uphy_dp_sel;
-};
-
-struct rockchip_typec_phy {
-   struct device *dev;
-   void __iomem *base;
-   struct extcon_dev *extcon;
-   struct regmap *grf_regs;
-   struct clk *clk_core;
-   struct clk *clk_ref;
-   struct reset_control *uphy_rst;
-   struct reset_control *pipe_rst;
-   struct reset_control *tcphy_rst;
-   const struct rockchip_usb3phy_port_cfg *port_cfgs;
-   /* mutex to protect access to individual PHYs */
-   struct mutex lock;
-
-   bool flip;
-   u8 mode;
-};
+#define DEFAULT_RATE   162000


DEFAULT_RATE seems a very common name for me, maybe add a prefix?

Okay, will fix it.




  struct phy_reg {
 u16 value;
@@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
 { 0x8,  CMN_DIAG_PLL0_LF_PROG },
  };

-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
 { 0xf0, CMN_PLL1_VCOCAL_INIT },
 { 0x18, CMN_PLL1_VCOCAL_ITER },
 { 0x30b9,

Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-08 Thread hl 



On Monday, May 07, 2018 09:59 PM, Enric Balletbo Serra wrote:

Hi Lin,

Thanks for the patch, apart from the new build warnings introduced
some more comments below.

2018-05-04 10:08 GMT+02:00 Lin Huang :

the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
  drivers/phy/rockchip/phy-rockchip-typec.c | 286 +++---
  include/soc/rockchip/rockchip_phy_typec.h |  72 
  2 files changed, 259 insertions(+), 99 deletions(-)
  create mode 100644 include/soc/rockchip/rockchip_phy_typec.h

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 76a4b58..831a93b 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -63,6 +63,7 @@

  #include 
  #include 
+#include 

  #define CMN_SSM_BANDGAP(0x21 << 2)
  #define CMN_SSM_BIAS   (0x22 << 2)
@@ -323,23 +324,31 @@
   * clock 0: PLL 0 div 1
   * clock 1: PLL 1 div 2
   */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
  #define CLK_PLL_MASK   0x33

  #define CMN_READY  BIT(0)

+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
  #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
  #define DP_PLL_ENABLE  BIT(0)
  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00

-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)

-#define PHY_MODE_SET_TIMEOUT   10
+#define PHY_MODE_SET_TIMEOUT   100


Why do you need to increase this timeout? Is because the software link
training timed out using the old value?

That for debug, will fix it in next version.




  #define PIN_ASSIGN_C_E 0x51d9
  #define PIN_ASSIGN_D_F 0x5100
@@ -349,51 +358,7 @@
  #define MODE_DFP_USB   BIT(1)
  #define MODE_DFP_DPBIT(2)

-struct usb3phy_reg {
-   u32 offset;
-   u32 enable_bit;
-   u32 write_enable;
-};
-
-/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
- * @reg: the base address for usb3-phy config.
- * @typec_conn_dir: the register of type-c connector direction.
- * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
- * @external_psm: the register of type-c phy external psm clock.
- * @pipe_status: the register of type-c phy pipe status.
- * @usb3_host_disable: the register of type-c usb3 host disable.
- * @usb3_host_port: the register of type-c usb3 host port.
- * @uphy_dp_sel: the register of type-c phy DP select control.
- */
-struct rockchip_usb3phy_port_cfg {
-   unsigned int reg;
-   struct usb3phy_reg typec_conn_dir;
-   struct usb3phy_reg usb3tousb2_en;
-   struct usb3phy_reg external_psm;
-   struct usb3phy_reg pipe_status;
-   struct usb3phy_reg usb3_host_disable;
-   struct usb3phy_reg usb3_host_port;
-   struct usb3phy_reg uphy_dp_sel;
-};
-
-struct rockchip_typec_phy {
-   struct device *dev;
-   void __iomem *base;
-   struct extcon_dev *extcon;
-   struct regmap *grf_regs;
-   struct clk *clk_core;
-   struct clk *clk_ref;
-   struct reset_control *uphy_rst;
-   struct reset_control *pipe_rst;
-   struct reset_control *tcphy_rst;
-   const struct rockchip_usb3phy_port_cfg *port_cfgs;
-   /* mutex to protect access to individual PHYs */
-   struct mutex lock;
-
-   bool flip;
-   u8 mode;
-};
+#define DEFAULT_RATE   162000


DEFAULT_RATE seems a very common name for me, maybe add a prefix?

Okay, will fix it.




  struct phy_reg {
 u16 value;
@@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
 { 0x8,  CMN_DIAG_PLL0_LF_PROG },
  };

-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
 { 0xf0, CMN_PLL1_VCOCAL_INIT },
 { 0x18, CMN_PLL1_VCOCAL_ITER },
 { 0x30b9,   CMN_PLL1_VCOCAL_START },
-   { 0x21c,CMN_PLL1_INTDIV },
+   {

Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-07 Thread Enric Balletbo Serra 
Hi Lin,

Thanks for the patch, apart from the new build warnings introduced
some more comments below.

2018-05-04 10:08 GMT+02:00 Lin Huang :
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
> Signed-off-by: Chris Zhong 
> Signed-off-by: Lin Huang 
> ---
>  drivers/phy/rockchip/phy-rockchip-typec.c | 286 
> +++---
>  include/soc/rockchip/rockchip_phy_typec.h |  72 
>  2 files changed, 259 insertions(+), 99 deletions(-)
>  create mode 100644 include/soc/rockchip/rockchip_phy_typec.h
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
> b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 76a4b58..831a93b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -63,6 +63,7 @@
>
>  #include 
>  #include 
> +#include 
>
>  #define CMN_SSM_BANDGAP(0x21 << 2)
>  #define CMN_SSM_BIAS   (0x22 << 2)
> @@ -323,23 +324,31 @@
>   * clock 0: PLL 0 div 1
>   * clock 1: PLL 1 div 2
>   */
> -#define CLK_PLL_CONFIG 0X30
> +#define CLK_PLL1_DIV1  0x20
> +#define CLK_PLL1_DIV2  0x30
>  #define CLK_PLL_MASK   0x33
>
>  #define CMN_READY  BIT(0)
>
> +#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
>  #define DP_PLL_CLOCK_ENABLEBIT(2)
> +#define DP_PLL_ENABLE_ACK  BIT(1)
>  #define DP_PLL_ENABLE  BIT(0)
>  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK  0xff00
>
> -#define DP_MODE_A0 BIT(4)
> -#define DP_MODE_A2 BIT(6)
> -#define DP_MODE_ENTER_A0   0xc101
> -#define DP_MODE_ENTER_A2   0xc104
> +#define DP_MODE_MASK   0xf
> +#define DP_MODE_ENTER_A0   BIT(0)
> +#define DP_MODE_ENTER_A2   BIT(2)
> +#define DP_MODE_ENTER_A3   BIT(3)
> +#define DP_MODE_A0_ACK BIT(4)
> +#define DP_MODE_A2_ACK BIT(6)
> +#define DP_MODE_A3_ACK BIT(7)
> +#define DP_LINK_RESET_DEASSERTED   BIT(8)
>
> -#define PHY_MODE_SET_TIMEOUT   10
> +#define PHY_MODE_SET_TIMEOUT   100
>

Why do you need to increase this timeout? Is because the software link
training timed out using the old value?


>  #define PIN_ASSIGN_C_E 0x51d9
>  #define PIN_ASSIGN_D_F 0x5100
> @@ -349,51 +358,7 @@
>  #define MODE_DFP_USB   BIT(1)
>  #define MODE_DFP_DPBIT(2)
>
> -struct usb3phy_reg {
> -   u32 offset;
> -   u32 enable_bit;
> -   u32 write_enable;
> -};
> -
> -/**
> - * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> - * @reg: the base address for usb3-phy config.
> - * @typec_conn_dir: the register of type-c connector direction.
> - * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> - * @external_psm: the register of type-c phy external psm clock.
> - * @pipe_status: the register of type-c phy pipe status.
> - * @usb3_host_disable: the register of type-c usb3 host disable.
> - * @usb3_host_port: the register of type-c usb3 host port.
> - * @uphy_dp_sel: the register of type-c phy DP select control.
> - */
> -struct rockchip_usb3phy_port_cfg {
> -   unsigned int reg;
> -   struct usb3phy_reg typec_conn_dir;
> -   struct usb3phy_reg usb3tousb2_en;
> -   struct usb3phy_reg external_psm;
> -   struct usb3phy_reg pipe_status;
> -   struct usb3phy_reg usb3_host_disable;
> -   struct usb3phy_reg usb3_host_port;
> -   struct usb3phy_reg uphy_dp_sel;
> -};
> -
> -struct rockchip_typec_phy {
> -   struct device *dev;
> -   void __iomem *base;
> -   struct extcon_dev *extcon;
> -   struct regmap *grf_regs;
> -   struct clk *clk_core;
> -   struct clk *clk_ref;
> -   struct reset_control *uphy_rst;
> -   struct reset_control *pipe_rst;
> -   struct reset_control *tcphy_rst;
> -   const struct rockchip_usb3phy_port_cfg *port_cfgs;
> -   /* mutex to protect access to individual PHYs */
> -   struct mutex lock;
> -
> -   bool flip;
> -   u8 mode;
> -};
> +#define DEFAULT_RATE   162000
>

DEFAULT_RATE seems a very common name for me, maybe add a prefix?


>  struct phy_reg {
> u16 value;
> @@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL0_LF_PROG },
>  };
>
> -struct phy_reg dp_pll_cfg[] = {
> +struct phy_reg dp_pll_rbr_cfg[] = {
> { 0xf0, CMN_PLL1_VCOCAL_INIT },
> { 0x18,

Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-07 Thread Enric Balletbo Serra 
Hi Lin,

Thanks for the patch, apart from the new build warnings introduced
some more comments below.

2018-05-04 10:08 GMT+02:00 Lin Huang :
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
> Signed-off-by: Chris Zhong 
> Signed-off-by: Lin Huang 
> ---
>  drivers/phy/rockchip/phy-rockchip-typec.c | 286 
> +++---
>  include/soc/rockchip/rockchip_phy_typec.h |  72 
>  2 files changed, 259 insertions(+), 99 deletions(-)
>  create mode 100644 include/soc/rockchip/rockchip_phy_typec.h
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
> b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 76a4b58..831a93b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -63,6 +63,7 @@
>
>  #include 
>  #include 
> +#include 
>
>  #define CMN_SSM_BANDGAP(0x21 << 2)
>  #define CMN_SSM_BIAS   (0x22 << 2)
> @@ -323,23 +324,31 @@
>   * clock 0: PLL 0 div 1
>   * clock 1: PLL 1 div 2
>   */
> -#define CLK_PLL_CONFIG 0X30
> +#define CLK_PLL1_DIV1  0x20
> +#define CLK_PLL1_DIV2  0x30
>  #define CLK_PLL_MASK   0x33
>
>  #define CMN_READY  BIT(0)
>
> +#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
>  #define DP_PLL_CLOCK_ENABLEBIT(2)
> +#define DP_PLL_ENABLE_ACK  BIT(1)
>  #define DP_PLL_ENABLE  BIT(0)
>  #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK  0xff00
>
> -#define DP_MODE_A0 BIT(4)
> -#define DP_MODE_A2 BIT(6)
> -#define DP_MODE_ENTER_A0   0xc101
> -#define DP_MODE_ENTER_A2   0xc104
> +#define DP_MODE_MASK   0xf
> +#define DP_MODE_ENTER_A0   BIT(0)
> +#define DP_MODE_ENTER_A2   BIT(2)
> +#define DP_MODE_ENTER_A3   BIT(3)
> +#define DP_MODE_A0_ACK BIT(4)
> +#define DP_MODE_A2_ACK BIT(6)
> +#define DP_MODE_A3_ACK BIT(7)
> +#define DP_LINK_RESET_DEASSERTED   BIT(8)
>
> -#define PHY_MODE_SET_TIMEOUT   10
> +#define PHY_MODE_SET_TIMEOUT   100
>

Why do you need to increase this timeout? Is because the software link
training timed out using the old value?


>  #define PIN_ASSIGN_C_E 0x51d9
>  #define PIN_ASSIGN_D_F 0x5100
> @@ -349,51 +358,7 @@
>  #define MODE_DFP_USB   BIT(1)
>  #define MODE_DFP_DPBIT(2)
>
> -struct usb3phy_reg {
> -   u32 offset;
> -   u32 enable_bit;
> -   u32 write_enable;
> -};
> -
> -/**
> - * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> - * @reg: the base address for usb3-phy config.
> - * @typec_conn_dir: the register of type-c connector direction.
> - * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> - * @external_psm: the register of type-c phy external psm clock.
> - * @pipe_status: the register of type-c phy pipe status.
> - * @usb3_host_disable: the register of type-c usb3 host disable.
> - * @usb3_host_port: the register of type-c usb3 host port.
> - * @uphy_dp_sel: the register of type-c phy DP select control.
> - */
> -struct rockchip_usb3phy_port_cfg {
> -   unsigned int reg;
> -   struct usb3phy_reg typec_conn_dir;
> -   struct usb3phy_reg usb3tousb2_en;
> -   struct usb3phy_reg external_psm;
> -   struct usb3phy_reg pipe_status;
> -   struct usb3phy_reg usb3_host_disable;
> -   struct usb3phy_reg usb3_host_port;
> -   struct usb3phy_reg uphy_dp_sel;
> -};
> -
> -struct rockchip_typec_phy {
> -   struct device *dev;
> -   void __iomem *base;
> -   struct extcon_dev *extcon;
> -   struct regmap *grf_regs;
> -   struct clk *clk_core;
> -   struct clk *clk_ref;
> -   struct reset_control *uphy_rst;
> -   struct reset_control *pipe_rst;
> -   struct reset_control *tcphy_rst;
> -   const struct rockchip_usb3phy_port_cfg *port_cfgs;
> -   /* mutex to protect access to individual PHYs */
> -   struct mutex lock;
> -
> -   bool flip;
> -   u8 mode;
> -};
> +#define DEFAULT_RATE   162000
>

DEFAULT_RATE seems a very common name for me, maybe add a prefix?


>  struct phy_reg {
> u16 value;
> @@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
> { 0x8,  CMN_DIAG_PLL0_LF_PROG },
>  };
>
> -struct phy_reg dp_pll_cfg[] = {
> +struct phy_reg dp_pll_rbr_cfg[] = {
> { 0xf0, CMN_PLL1_VCOCAL_INIT },
> { 0x18, CMN_PLL1_VCOCAL_ITER },
> { 0x30b9,

Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-04 Thread kbuild test robot 
Hi Lin,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on v4.17-rc3 next-20180504]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Lin-Huang/drm-rockchip-add-transfer-function-for-cdn-dp/20180504-235745
base:   
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git 
for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All warnings (new ones prefixed by >>):

   drivers/phy/rockchip/phy-rockchip-typec.c: In function 
'rockchip_typec_phy_probe':
>> drivers/phy/rockchip/phy-rockchip-typec.c:1227:21: warning: assignment 
>> discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
   tcphy->port_cfgs = _cfgs[index];
^
   drivers/phy/rockchip/phy-rockchip-typec.c: In function 
'tcphy_cfg_dp_pll.isra.2':
>> drivers/phy/rockchip/phy-rockchip-typec.c:512:6: warning: 'clk_ctrl' may be 
>> used uninitialized in this function [-Wmaybe-uninitialized]
 u32 clk_ctrl;
 ^~~~
>> drivers/phy/rockchip/phy-rockchip-typec.c:511:18: warning: 'phy_cfg' may be 
>> used uninitialized in this function [-Wmaybe-uninitialized]
 struct phy_reg *phy_cfg;
 ^~~

vim +/const +1227 drivers/phy/rockchip/phy-rockchip-typec.c

e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1194  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1195  static int rockchip_typec_phy_probe(struct platform_device 
*pdev)
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1196  {
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1197  struct device *dev = >dev;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1198  struct device_node *np = dev->of_node;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1199  struct device_node *child_np;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1200  struct rockchip_typec_phy *tcphy;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1201  struct phy_provider *phy_provider;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1202  struct resource *res;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1203  const struct rockchip_usb3phy_port_cfg *phy_cfgs;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1204  const struct of_device_id *match;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1205  int index, ret;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1206  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1207  tcphy = devm_kzalloc(dev, sizeof(*tcphy), GFP_KERNEL);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1208  if (!tcphy)
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1209  return -ENOMEM;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1210  
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1211  match = of_match_device(dev->driver->of_match_table, dev);
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1212  if (!match || !match->data) {
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1213  dev_err(dev, "phy configs are not assigned!\n");
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1214  return -EINVAL;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1215  }
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1216  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1217  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1218  tcphy->base = devm_ioremap_resource(dev, res);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1219  if (IS_ERR(tcphy->base))
e96be45c drivers/phy/phy-rockchip-typec.c

Re: [PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-04 Thread kbuild test robot 
Hi Lin,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on v4.17-rc3 next-20180504]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Lin-Huang/drm-rockchip-add-transfer-function-for-cdn-dp/20180504-235745
base:   
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git 
for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All warnings (new ones prefixed by >>):

   drivers/phy/rockchip/phy-rockchip-typec.c: In function 
'rockchip_typec_phy_probe':
>> drivers/phy/rockchip/phy-rockchip-typec.c:1227:21: warning: assignment 
>> discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
   tcphy->port_cfgs = _cfgs[index];
^
   drivers/phy/rockchip/phy-rockchip-typec.c: In function 
'tcphy_cfg_dp_pll.isra.2':
>> drivers/phy/rockchip/phy-rockchip-typec.c:512:6: warning: 'clk_ctrl' may be 
>> used uninitialized in this function [-Wmaybe-uninitialized]
 u32 clk_ctrl;
 ^~~~
>> drivers/phy/rockchip/phy-rockchip-typec.c:511:18: warning: 'phy_cfg' may be 
>> used uninitialized in this function [-Wmaybe-uninitialized]
 struct phy_reg *phy_cfg;
 ^~~

vim +/const +1227 drivers/phy/rockchip/phy-rockchip-typec.c

e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1194  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1195  static int rockchip_typec_phy_probe(struct platform_device 
*pdev)
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1196  {
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1197  struct device *dev = >dev;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1198  struct device_node *np = dev->of_node;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1199  struct device_node *child_np;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1200  struct rockchip_typec_phy *tcphy;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1201  struct phy_provider *phy_provider;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1202  struct resource *res;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1203  const struct rockchip_usb3phy_port_cfg *phy_cfgs;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1204  const struct of_device_id *match;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1205  int index, ret;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1206  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1207  tcphy = devm_kzalloc(dev, sizeof(*tcphy), GFP_KERNEL);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1208  if (!tcphy)
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1209  return -ENOMEM;
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1210  
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1211  match = of_match_device(dev->driver->of_match_table, dev);
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1212  if (!match || !match->data) {
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1213  dev_err(dev, "phy configs are not assigned!\n");
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1214  return -EINVAL;
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1215  }
0fbc47d9 drivers/phy/rockchip/phy-rockchip-typec.c Enric Balletbo i Serra 
2018-02-16  1216  
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1217  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1218  tcphy->base = devm_ioremap_resource(dev, res);
e96be45c drivers/phy/phy-rockchip-typec.c  Chris Zhong
2016-08-23  1219  if (IS_ERR(tcphy->base))
e96be45c drivers/phy/phy-rockchip-typec.c

[PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-04 Thread Lin Huang 
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
 drivers/phy/rockchip/phy-rockchip-typec.c | 286 +++---
 include/soc/rockchip/rockchip_phy_typec.h |  72 
 2 files changed, 259 insertions(+), 99 deletions(-)
 create mode 100644 include/soc/rockchip/rockchip_phy_typec.h

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 76a4b58..831a93b 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -63,6 +63,7 @@
 
 #include 
 #include 
+#include 
 
 #define CMN_SSM_BANDGAP(0x21 << 2)
 #define CMN_SSM_BIAS   (0x22 << 2)
@@ -323,23 +324,31 @@
  * clock 0: PLL 0 div 1
  * clock 1: PLL 1 div 2
  */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
 #define CLK_PLL_MASK   0x33
 
 #define CMN_READY  BIT(0)
 
+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
 #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
 #define DP_PLL_ENABLE  BIT(0)
 #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00
 
-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)
 
-#define PHY_MODE_SET_TIMEOUT   10
+#define PHY_MODE_SET_TIMEOUT   100
 
 #define PIN_ASSIGN_C_E 0x51d9
 #define PIN_ASSIGN_D_F 0x5100
@@ -349,51 +358,7 @@
 #define MODE_DFP_USB   BIT(1)
 #define MODE_DFP_DPBIT(2)
 
-struct usb3phy_reg {
-   u32 offset;
-   u32 enable_bit;
-   u32 write_enable;
-};
-
-/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
- * @reg: the base address for usb3-phy config.
- * @typec_conn_dir: the register of type-c connector direction.
- * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
- * @external_psm: the register of type-c phy external psm clock.
- * @pipe_status: the register of type-c phy pipe status.
- * @usb3_host_disable: the register of type-c usb3 host disable.
- * @usb3_host_port: the register of type-c usb3 host port.
- * @uphy_dp_sel: the register of type-c phy DP select control.
- */
-struct rockchip_usb3phy_port_cfg {
-   unsigned int reg;
-   struct usb3phy_reg typec_conn_dir;
-   struct usb3phy_reg usb3tousb2_en;
-   struct usb3phy_reg external_psm;
-   struct usb3phy_reg pipe_status;
-   struct usb3phy_reg usb3_host_disable;
-   struct usb3phy_reg usb3_host_port;
-   struct usb3phy_reg uphy_dp_sel;
-};
-
-struct rockchip_typec_phy {
-   struct device *dev;
-   void __iomem *base;
-   struct extcon_dev *extcon;
-   struct regmap *grf_regs;
-   struct clk *clk_core;
-   struct clk *clk_ref;
-   struct reset_control *uphy_rst;
-   struct reset_control *pipe_rst;
-   struct reset_control *tcphy_rst;
-   const struct rockchip_usb3phy_port_cfg *port_cfgs;
-   /* mutex to protect access to individual PHYs */
-   struct mutex lock;
-
-   bool flip;
-   u8 mode;
-};
+#define DEFAULT_RATE   162000
 
 struct phy_reg {
u16 value;
@@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL0_LF_PROG },
 };
 
-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9,   CMN_PLL1_VCOCAL_START },
-   { 0x21c,CMN_PLL1_INTDIV },
+   { 0x87, CMN_PLL1_INTDIV },
{ 0,CMN_PLL1_FRACDIV },
-   { 0x5,  CMN_PLL1_HIGH_THR },
-   { 0x35, CMN_PLL1_SS_CTRL1 },
-   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
+   { 0x22, CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0,CMN_PLLSM1_USER_DEF_CTRL },

[PATCH 2/4] phy: rockchip-typec: support variable phy config value

2018-05-04 Thread Lin Huang 
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.

Signed-off-by: Chris Zhong 
Signed-off-by: Lin Huang 
---
 drivers/phy/rockchip/phy-rockchip-typec.c | 286 +++---
 include/soc/rockchip/rockchip_phy_typec.h |  72 
 2 files changed, 259 insertions(+), 99 deletions(-)
 create mode 100644 include/soc/rockchip/rockchip_phy_typec.h

diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
b/drivers/phy/rockchip/phy-rockchip-typec.c
index 76a4b58..831a93b 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -63,6 +63,7 @@
 
 #include 
 #include 
+#include 
 
 #define CMN_SSM_BANDGAP(0x21 << 2)
 #define CMN_SSM_BIAS   (0x22 << 2)
@@ -323,23 +324,31 @@
  * clock 0: PLL 0 div 1
  * clock 1: PLL 1 div 2
  */
-#define CLK_PLL_CONFIG 0X30
+#define CLK_PLL1_DIV1  0x20
+#define CLK_PLL1_DIV2  0x30
 #define CLK_PLL_MASK   0x33
 
 #define CMN_READY  BIT(0)
 
+#define DP_PLL_CLOCK_ENABLE_ACKBIT(3)
 #define DP_PLL_CLOCK_ENABLEBIT(2)
+#define DP_PLL_ENABLE_ACK  BIT(1)
 #define DP_PLL_ENABLE  BIT(0)
 #define DP_PLL_DATA_RATE_RBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR   ((2 << 12) | (4 << 8))
 #define DP_PLL_DATA_RATE_HBR2  ((1 << 12) | (2 << 8))
+#define DP_PLL_DATA_RATE_MASK  0xff00
 
-#define DP_MODE_A0 BIT(4)
-#define DP_MODE_A2 BIT(6)
-#define DP_MODE_ENTER_A0   0xc101
-#define DP_MODE_ENTER_A2   0xc104
+#define DP_MODE_MASK   0xf
+#define DP_MODE_ENTER_A0   BIT(0)
+#define DP_MODE_ENTER_A2   BIT(2)
+#define DP_MODE_ENTER_A3   BIT(3)
+#define DP_MODE_A0_ACK BIT(4)
+#define DP_MODE_A2_ACK BIT(6)
+#define DP_MODE_A3_ACK BIT(7)
+#define DP_LINK_RESET_DEASSERTED   BIT(8)
 
-#define PHY_MODE_SET_TIMEOUT   10
+#define PHY_MODE_SET_TIMEOUT   100
 
 #define PIN_ASSIGN_C_E 0x51d9
 #define PIN_ASSIGN_D_F 0x5100
@@ -349,51 +358,7 @@
 #define MODE_DFP_USB   BIT(1)
 #define MODE_DFP_DPBIT(2)
 
-struct usb3phy_reg {
-   u32 offset;
-   u32 enable_bit;
-   u32 write_enable;
-};
-
-/**
- * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
- * @reg: the base address for usb3-phy config.
- * @typec_conn_dir: the register of type-c connector direction.
- * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
- * @external_psm: the register of type-c phy external psm clock.
- * @pipe_status: the register of type-c phy pipe status.
- * @usb3_host_disable: the register of type-c usb3 host disable.
- * @usb3_host_port: the register of type-c usb3 host port.
- * @uphy_dp_sel: the register of type-c phy DP select control.
- */
-struct rockchip_usb3phy_port_cfg {
-   unsigned int reg;
-   struct usb3phy_reg typec_conn_dir;
-   struct usb3phy_reg usb3tousb2_en;
-   struct usb3phy_reg external_psm;
-   struct usb3phy_reg pipe_status;
-   struct usb3phy_reg usb3_host_disable;
-   struct usb3phy_reg usb3_host_port;
-   struct usb3phy_reg uphy_dp_sel;
-};
-
-struct rockchip_typec_phy {
-   struct device *dev;
-   void __iomem *base;
-   struct extcon_dev *extcon;
-   struct regmap *grf_regs;
-   struct clk *clk_core;
-   struct clk *clk_ref;
-   struct reset_control *uphy_rst;
-   struct reset_control *pipe_rst;
-   struct reset_control *tcphy_rst;
-   const struct rockchip_usb3phy_port_cfg *port_cfgs;
-   /* mutex to protect access to individual PHYs */
-   struct mutex lock;
-
-   bool flip;
-   u8 mode;
-};
+#define DEFAULT_RATE   162000
 
 struct phy_reg {
u16 value;
@@ -417,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
{ 0x8,  CMN_DIAG_PLL0_LF_PROG },
 };
 
-struct phy_reg dp_pll_cfg[] = {
+struct phy_reg dp_pll_rbr_cfg[] = {
{ 0xf0, CMN_PLL1_VCOCAL_INIT },
{ 0x18, CMN_PLL1_VCOCAL_ITER },
{ 0x30b9,   CMN_PLL1_VCOCAL_START },
-   { 0x21c,CMN_PLL1_INTDIV },
+   { 0x87, CMN_PLL1_INTDIV },
{ 0,CMN_PLL1_FRACDIV },
-   { 0x5,  CMN_PLL1_HIGH_THR },
-   { 0x35, CMN_PLL1_SS_CTRL1 },
-   { 0x7f1e,   CMN_PLL1_SS_CTRL2 },
+   { 0x22, CMN_PLL1_HIGH_THR },
+   { 0x8000,   CMN_PLL1_SS_CTRL1 },
+   { 0,CMN_PLL1_SS_CTRL2 },
{ 0x20, CMN_PLL1_DSM_DIAG },
{ 0,CMN_PLLSM1_USER_DEF_CTRL },
{ 0,