Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
On Sun, Oct 20, 2019 at 11:47 PM Alexander Sverdlin wrote: > On 20/10/2019 13:49, Arnd Bergmann wrote: > >>> Ah, that makes sense. so all interrupt numbers need to > >>> be shifted by a fixed number (e.g. 1) like we did for > >>> other platforms (see attachment). > >> Yes, the below patch resolved both GPIO and DMA issues. > ^^^ > >> Previous patch (selecting IRQ_DOMAIN_HIERARCHY) is not > >> required. > >> > >> If you re-spin all 3 ep93xx-relevant patches together, you can put my > >> Tested-by: Alexander Sverdlin > >> on them. > > Awesome, thanks for testing. > > > > I only remember sending two patches for ep93xx: > > ARM: ep93xx: make mach/ep93xx-regs.h local > > ARM: ep93xx: enable SPARSE_IRQ > > > > and have added the Tested-by tag to them now. Is there a third one > > I missed? > > The patch shifting the IRQ-numbering by one is a prerequisite for the two > above patches, right? Ah, now I see what you mean. I had folded that change into the sparse-irq change, but you are right that it makes more sense as a separate changeset before the other ones. Changing that now. Thanks, Arnd
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
Hi! On 20/10/2019 13:49, Arnd Bergmann wrote: >>> Ah, that makes sense. so all interrupt numbers need to >>> be shifted by a fixed number (e.g. 1) like we did for >>> other platforms (see attachment). >> Yes, the below patch resolved both GPIO and DMA issues. ^^^ >> Previous patch (selecting IRQ_DOMAIN_HIERARCHY) is not >> required. >> >> If you re-spin all 3 ep93xx-relevant patches together, you can put my >> Tested-by: Alexander Sverdlin >> on them. > Awesome, thanks for testing. > > I only remember sending two patches for ep93xx: > ARM: ep93xx: make mach/ep93xx-regs.h local > ARM: ep93xx: enable SPARSE_IRQ > > and have added the Tested-by tag to them now. Is there a third one > I missed? The patch shifting the IRQ-numbering by one is a prerequisite for the two above patches, right? -- Alex.
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
On Sat, Oct 19, 2019 at 11:14 PM Alexander Sverdlin wrote: > On Sat, 19 Oct 2019 22:44:18 +0200 > Arnd Bergmann wrote: > > Ah, that makes sense. so all interrupt numbers need to > > be shifted by a fixed number (e.g. 1) like we did for > > other platforms (see attachment). > > Yes, the below patch resolved both GPIO and DMA issues. > Previous patch (selecting IRQ_DOMAIN_HIERARCHY) is not > required. > > If you re-spin all 3 ep93xx-relevant patches together, you can put my > Tested-by: Alexander Sverdlin > on them. Awesome, thanks for testing. I only remember sending two patches for ep93xx: ARM: ep93xx: make mach/ep93xx-regs.h local ARM: ep93xx: enable SPARSE_IRQ and have added the Tested-by tag to them now. Is there a third one I missed? Arnd
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
Hi!
On Sat, 19 Oct 2019 22:44:18 +0200
Arnd Bergmann wrote:
> > > > # cat /proc/interrupts
> > > >CPU0
> > > > 39:146 VIC 7 Edge eth0
> > > > 51: 162161 VIC 19 Edge ep93xx timer
> > > > 52:139 VIC 20 Edge uart-pl010
> > > > 53: 4 VIC 21 Edge ep93xx-spi
> > > > 60: 0 VIC 28 Edge ep93xx-i2s
> > > > Err: 0
> > >
> > > I guess that is partial success: some irqs do work ;-)
> >
> > Yep, VIC1 is working, while VIC0 is not.
> >
> > > The two interrupts that did not get registered are for the
> > > dmaengine driver, and that makes sense given the error
> > > message about the DMA not working. No idea how
> > > that would be a result of the irq changes though.
> >
> > Seems, that it has exposed some incompatibilities of
> > starting IRQ 0 in EP93xx platform fir VIC0 and VIC code
> > itself, which assumes 0 means "auto assignment" (refer
> > to vic_init()).
>
> Ah, that makes sense. so all interrupt numbers need to
> be shifted by a fixed number (e.g. 1) like we did for
> other platforms (see attachment).
Yes, the below patch resolved both GPIO and DMA issues.
Previous patch (selecting IRQ_DOMAIN_HIERARCHY) is not
required.
If you re-spin all 3 ep93xx-relevant patches together, you can put my
Tested-by: Alexander Sverdlin
on them.
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 6fb19a393fd2..f0a71d4e076f 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -47,6 +47,7 @@
> #include
>
> #include "soc.h"
> +#include "irqs.h"
>
> /*
> * Static I/O mappings that are needed for all EP93xx platforms
> @@ -75,8 +76,8 @@ void __init ep93xx_map_io(void)
> */
> void __init ep93xx_init_irq(void)
> {
> - vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
> - vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
> + vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK,
> 0);
> + vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK,
> 0);
> }
>
>
> diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h
> index 3ffdb3a2f3e4..353201b90c66 100644
> --- a/arch/arm/mach-ep93xx/irqs.h
> +++ b/arch/arm/mach-ep93xx/irqs.h
> @@ -2,69 +2,73 @@
> #ifndef __ASM_ARCH_IRQS_H
> #define __ASM_ARCH_IRQS_H
>
> -#define IRQ_EP93XX_COMMRX2
> -#define IRQ_EP93XX_COMMTX3
> -#define IRQ_EP93XX_TIMER14
> -#define IRQ_EP93XX_TIMER25
> -#define IRQ_EP93XX_AACINTR 6
> -#define IRQ_EP93XX_DMAM2P0 7
> -#define IRQ_EP93XX_DMAM2P1 8
> -#define IRQ_EP93XX_DMAM2P2 9
> -#define IRQ_EP93XX_DMAM2P3 10
> -#define IRQ_EP93XX_DMAM2P4 11
> -#define IRQ_EP93XX_DMAM2P5 12
> -#define IRQ_EP93XX_DMAM2P6 13
> -#define IRQ_EP93XX_DMAM2P7 14
> -#define IRQ_EP93XX_DMAM2P8 15
> -#define IRQ_EP93XX_DMAM2P9 16
> -#define IRQ_EP93XX_DMAM2M0 17
> -#define IRQ_EP93XX_DMAM2M1 18
> -#define IRQ_EP93XX_GPIO0MUX 19
> -#define IRQ_EP93XX_GPIO1MUX 20
> -#define IRQ_EP93XX_GPIO2MUX 21
> -#define IRQ_EP93XX_GPIO3MUX 22
> -#define IRQ_EP93XX_UART1RX 23
> -#define IRQ_EP93XX_UART1TX 24
> -#define IRQ_EP93XX_UART2RX 25
> -#define IRQ_EP93XX_UART2TX 26
> -#define IRQ_EP93XX_UART3RX 27
> -#define IRQ_EP93XX_UART3TX 28
> -#define IRQ_EP93XX_KEY 29
> -#define IRQ_EP93XX_TOUCH 30
> +#define IRQ_EP93XX_VIC0 1
> +
> +#define IRQ_EP93XX_COMMRX(IRQ_EP93XX_VIC0 + 2)
> +#define IRQ_EP93XX_COMMTX(IRQ_EP93XX_VIC0 + 3)
> +#define IRQ_EP93XX_TIMER1(IRQ_EP93XX_VIC0 + 4)
> +#define IRQ_EP93XX_TIMER2(IRQ_EP93XX_VIC0 + 5)
> +#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
> +#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
> +#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
> +#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
> +#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
> +#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
> +#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
> +#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
> +#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
> +#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
> +#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
> +#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
> +#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
> +#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
> +#define
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
On Sat, Oct 19, 2019 at 10:24 PM Alexander Sverdlin
wrote:
> On Sat, 19 Oct 2019 22:08:40 +0200
> Arnd Bergmann wrote:
>
> > > # cat /proc/interrupts
> > >CPU0
> > > 39:146 VIC 7 Edge eth0
> > > 51: 162161 VIC 19 Edge ep93xx timer
> > > 52:139 VIC 20 Edge uart-pl010
> > > 53: 4 VIC 21 Edge ep93xx-spi
> > > 60: 0 VIC 28 Edge ep93xx-i2s
> > > Err: 0
> >
> > I guess that is partial success: some irqs do work ;-)
>
> Yep, VIC1 is working, while VIC0 is not.
>
> > The two interrupts that did not get registered are for the
> > dmaengine driver, and that makes sense given the error
> > message about the DMA not working. No idea how
> > that would be a result of the irq changes though.
>
> Seems, that it has exposed some incompatibilities of
> starting IRQ 0 in EP93xx platform fir VIC0 and VIC code
> itself, which assumes 0 means "auto assignment" (refer
> to vic_init()).
Ah, that makes sense. so all interrupt numbers need to
be shifted by a fixed number (e.g. 1) like we did for
other platforms (see attachment).
Arnd
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 6fb19a393fd2..f0a71d4e076f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -47,6 +47,7 @@
#include
#include "soc.h"
+#include "irqs.h"
/*
* Static I/O mappings that are needed for all EP93xx platforms
@@ -75,8 +76,8 @@ void __init ep93xx_map_io(void)
*/
void __init ep93xx_init_irq(void)
{
- vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
- vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
+ vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
+ vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0);
}
diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h
index 3ffdb3a2f3e4..353201b90c66 100644
--- a/arch/arm/mach-ep93xx/irqs.h
+++ b/arch/arm/mach-ep93xx/irqs.h
@@ -2,69 +2,73 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
-#define IRQ_EP93XX_COMMRX 2
-#define IRQ_EP93XX_COMMTX 3
-#define IRQ_EP93XX_TIMER1 4
-#define IRQ_EP93XX_TIMER2 5
-#define IRQ_EP93XX_AACINTR 6
-#define IRQ_EP93XX_DMAM2P0 7
-#define IRQ_EP93XX_DMAM2P1 8
-#define IRQ_EP93XX_DMAM2P2 9
-#define IRQ_EP93XX_DMAM2P3 10
-#define IRQ_EP93XX_DMAM2P4 11
-#define IRQ_EP93XX_DMAM2P5 12
-#define IRQ_EP93XX_DMAM2P6 13
-#define IRQ_EP93XX_DMAM2P7 14
-#define IRQ_EP93XX_DMAM2P8 15
-#define IRQ_EP93XX_DMAM2P9 16
-#define IRQ_EP93XX_DMAM2M0 17
-#define IRQ_EP93XX_DMAM2M1 18
-#define IRQ_EP93XX_GPIO0MUX 19
-#define IRQ_EP93XX_GPIO1MUX 20
-#define IRQ_EP93XX_GPIO2MUX 21
-#define IRQ_EP93XX_GPIO3MUX 22
-#define IRQ_EP93XX_UART1RX 23
-#define IRQ_EP93XX_UART1TX 24
-#define IRQ_EP93XX_UART2RX 25
-#define IRQ_EP93XX_UART2TX 26
-#define IRQ_EP93XX_UART3RX 27
-#define IRQ_EP93XX_UART3TX 28
-#define IRQ_EP93XX_KEY 29
-#define IRQ_EP93XX_TOUCH 30
+#define IRQ_EP93XX_VIC0 1
+
+#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2)
+#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3)
+#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4)
+#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5)
+#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6)
+#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7)
+#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8)
+#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9)
+#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10)
+#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11)
+#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12)
+#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13)
+#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14)
+#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15)
+#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16)
+#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17)
+#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18)
+#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19)
+#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20)
+#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21)
+#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22)
+#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23)
+#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24)
+#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25)
+#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26)
+#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27)
+#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28)
+#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29)
+#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30)
#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffc
-#define IRQ_EP93XX_EXT0 32
-#define IRQ_EP93XX_EXT1 33
-#define IRQ_EP93XX_EXT2 34
-#define IRQ_EP93XX_64HZ 35
-#define IRQ_EP93XX_WATCHDOG 36
-#define IRQ_EP93XX_RTC 37
-#define IRQ_EP93XX_IRDA 38
-#define IRQ_EP93XX_ETHERNET 39
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
Hi! On Sat, 19 Oct 2019 22:08:40 +0200 Arnd Bergmann wrote: > > # cat /proc/interrupts > >CPU0 > > 39:146 VIC 7 Edge eth0 > > 51: 162161 VIC 19 Edge ep93xx timer > > 52:139 VIC 20 Edge uart-pl010 > > 53: 4 VIC 21 Edge ep93xx-spi > > 60: 0 VIC 28 Edge ep93xx-i2s > > Err: 0 > > I guess that is partial success: some irqs do work ;-) Yep, VIC1 is working, while VIC0 is not. > The two interrupts that did not get registered are for the > dmaengine driver, and that makes sense given the error > message about the DMA not working. No idea how > that would be a result of the irq changes though. Seems, that it has exposed some incompatibilities of starting IRQ 0 in EP93xx platform fir VIC0 and VIC code itself, which assumes 0 means "auto assignment" (refer to vic_init()). But there are more problems I didn't resolve yet. -- Alexander Sverdlin.
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
On Sat, Oct 19, 2019 at 6:43 PM Alexander Sverdlin wrote: > On Fri, 18 Oct 2019 18:29:15 +0200 > Arnd Bergmann wrote: > > > Without CONFIG_SPARSE_IRQ, we rely on mach/irqs.h to define NR_IRQS > > globally. Do the minimal conversion by setting .nr_irqs in each > > machine descriptor. > > > > Only the vision_ep9307 machine has extra IRQs for GPIOs, so make > > .nr_irqs the original value there, while using the plain NR_EP93XX_IRQS > > everywhere else. > > This patch causes multiple problems on EDB9302: > > 1. WARNINGs during gpiochip registration, for instance: > > [ cut here ] > WARNING: CPU: 0 PID: 1 at kernel/irq/chip.c:1013 > __irq_do_set_handler+0x94/0x188 > CPU: 0 PID: 1 Comm: swapper Tainted: GW 5.4.0-rc3 #1 > Hardware name: Cirrus Logic EDB9302 Evaluation Board > [] (unwind_backtrace) from [] (show_stack+0x10/0x18) > [] (show_stack) from [] (dump_stack+0x18/0x24) > [] (dump_stack) from [] (__warn+0xa4/0xc8) > [] (__warn) from [] (warn_slowpath_fmt+0xa8/0xb8) > [] (warn_slowpath_fmt) from [] > (__irq_do_set_handler+0x94/0x188) > [] (__irq_do_set_handler) from [] > (irq_set_chained_handler_and_data+0x48/0x7c) > [] (irq_set_chained_handler_and_data) from [] > (gpiochip_add_data_with_key+0x6d4/0xabc) > [] (gpiochip_add_data_with_key) from [] > (devm_gpiochip_add_data+0x40/0x88) > [] (devm_gpiochip_add_data) from [] > (ep93xx_gpio_probe+0x1ac/0x280) > [] (ep93xx_gpio_probe) from [] > (platform_drv_probe+0x28/0x6c) > [] (platform_drv_probe) from [] (really_probe+0x1c8/0x340) > [] (really_probe) from [] (bus_for_each_drv+0x58/0xc0) > [] (bus_for_each_drv) from [] (__device_attach+0xb4/0x104) > [] (__device_attach) from [] (bus_probe_device+0x8c/0x94) > [] (bus_probe_device) from [] (device_add+0x3d0/0x59c) > [] (device_add) from [] (platform_device_add+0x100/0x20c) > [] (platform_device_add) from [] > (ep93xx_init_devices+0x16c/0x20c) > [] (ep93xx_init_devices) from [] > (edb93xx_init_machine+0xc/0x84) > [] (edb93xx_init_machine) from [] > (customize_machine+0x20/0x38) > [] (customize_machine) from [] > (do_one_initcall+0x78/0x1a0) > [] (do_one_initcall) from [] > (kernel_init_freeable+0x104/0x1b8) > [] (kernel_init_freeable) from [] (kernel_init+0x8/0xf8) > [] (kernel_init) from [] (ret_from_fork+0x14/0x24) > Exception stack(0xc4433fb0 to 0xc4433ff8) > 3fa0: > 3fc0: > 3fe0: 0013 > ---[ end trace 8f9e35e2d6224882 ]--- My first guess would be that this is just the missing irq domain code: diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 38e096e6925f..7c195af6f75d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -205,6 +205,7 @@ config GPIO_EP93XX depends on ARCH_EP93XX select GPIO_GENERIC select GPIOLIB_IRQCHIP + select IRQ_DOMAIN_HIERARCHY config GPIO_EXAR tristate "Support for GPIO pins on XR17V352/354/358" But most likely there are more changes required to the gpio code. > 2. Broken sound (I2S), this looks like below in the log: > > ep93xx-i2s ep93xx-i2s: Missing dma channel for stream: 0 > CS4271: ASoC: pcm constructor failed: -22 > edb93xx-audio edb93xx-audio: ASoC: can't create pcm CS4271 HiFi :-22 > > And /proc/interrupts has two entries less. Without patch: > > # cat /proc/interrupts >CPU0 > 7: 0 VIC 7 Edge i2s-pcm-out > 8: 0 VIC 8 Edge i2s-pcm-in > 39: 2 VIC 7 Edge eth0 > 51: 7532 VIC 19 Edge ep93xx timer > 52:144 VIC 20 Edge uart-pl010 > 53: 4 VIC 21 Edge ep93xx-spi > 60: 0 VIC 28 Edge ep93xx-i2s > Err: 0 > > With patch: > > # cat /proc/interrupts >CPU0 > 39:146 VIC 7 Edge eth0 > 51: 162161 VIC 19 Edge ep93xx timer > 52:139 VIC 20 Edge uart-pl010 > 53: 4 VIC 21 Edge ep93xx-spi > 60: 0 VIC 28 Edge ep93xx-i2s > Err: 0 I guess that is partial success: some irqs do work ;-) The two interrupts that did not get registered are for the dmaengine driver, and that makes sense given the error message about the DMA not working. No idea how that would be a result of the irq changes though. > I will try to look into I2S problem... Thanks! Arnd
Re: [PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
Hello Arnd,
On Fri, 18 Oct 2019 18:29:15 +0200
Arnd Bergmann wrote:
> Without CONFIG_SPARSE_IRQ, we rely on mach/irqs.h to define NR_IRQS
> globally. Do the minimal conversion by setting .nr_irqs in each
> machine descriptor.
>
> Only the vision_ep9307 machine has extra IRQs for GPIOs, so make
> .nr_irqs the original value there, while using the plain NR_EP93XX_IRQS
> everywhere else.
This patch causes multiple problems on EDB9302:
1. WARNINGs during gpiochip registration, for instance:
[ cut here ]
WARNING: CPU: 0 PID: 1 at kernel/irq/chip.c:1013 __irq_do_set_handler+0x94/0x188
CPU: 0 PID: 1 Comm: swapper Tainted: GW 5.4.0-rc3 #1
Hardware name: Cirrus Logic EDB9302 Evaluation Board
[] (unwind_backtrace) from [] (show_stack+0x10/0x18)
[] (show_stack) from [] (dump_stack+0x18/0x24)
[] (dump_stack) from [] (__warn+0xa4/0xc8)
[] (__warn) from [] (warn_slowpath_fmt+0xa8/0xb8)
[] (warn_slowpath_fmt) from []
(__irq_do_set_handler+0x94/0x188)
[] (__irq_do_set_handler) from []
(irq_set_chained_handler_and_data+0x48/0x7c)
[] (irq_set_chained_handler_and_data) from []
(gpiochip_add_data_with_key+0x6d4/0xabc)
[] (gpiochip_add_data_with_key) from []
(devm_gpiochip_add_data+0x40/0x88)
[] (devm_gpiochip_add_data) from []
(ep93xx_gpio_probe+0x1ac/0x280)
[] (ep93xx_gpio_probe) from []
(platform_drv_probe+0x28/0x6c)
[] (platform_drv_probe) from [] (really_probe+0x1c8/0x340)
[] (really_probe) from [] (bus_for_each_drv+0x58/0xc0)
[] (bus_for_each_drv) from [] (__device_attach+0xb4/0x104)
[] (__device_attach) from [] (bus_probe_device+0x8c/0x94)
[] (bus_probe_device) from [] (device_add+0x3d0/0x59c)
[] (device_add) from [] (platform_device_add+0x100/0x20c)
[] (platform_device_add) from []
(ep93xx_init_devices+0x16c/0x20c)
[] (ep93xx_init_devices) from []
(edb93xx_init_machine+0xc/0x84)
[] (edb93xx_init_machine) from []
(customize_machine+0x20/0x38)
[] (customize_machine) from [] (do_one_initcall+0x78/0x1a0)
[] (do_one_initcall) from []
(kernel_init_freeable+0x104/0x1b8)
[] (kernel_init_freeable) from [] (kernel_init+0x8/0xf8)
[] (kernel_init) from [] (ret_from_fork+0x14/0x24)
Exception stack(0xc4433fb0 to 0xc4433ff8)
3fa0:
3fc0:
3fe0: 0013
---[ end trace 8f9e35e2d6224882 ]---
2. Broken sound (I2S), this looks like below in the log:
ep93xx-i2s ep93xx-i2s: Missing dma channel for stream: 0
CS4271: ASoC: pcm constructor failed: -22
edb93xx-audio edb93xx-audio: ASoC: can't create pcm CS4271 HiFi :-22
And /proc/interrupts has two entries less. Without patch:
# cat /proc/interrupts
CPU0
7: 0 VIC 7 Edge i2s-pcm-out
8: 0 VIC 8 Edge i2s-pcm-in
39: 2 VIC 7 Edge eth0
51: 7532 VIC 19 Edge ep93xx timer
52:144 VIC 20 Edge uart-pl010
53: 4 VIC 21 Edge ep93xx-spi
60: 0 VIC 28 Edge ep93xx-i2s
Err: 0
With patch:
# cat /proc/interrupts
CPU0
39:146 VIC 7 Edge eth0
51: 162161 VIC 19 Edge ep93xx timer
52:139 VIC 20 Edge uart-pl010
53: 4 VIC 21 Edge ep93xx-spi
60: 0 VIC 28 Edge ep93xx-i2s
Err: 0
I will try to look into I2S problem...
> ---
> It's been a while since I did this, no idea what else is needed
> here or if this is correct at all.
>
> Cc: Hartley Sweeten
> Cc: Alexander Sverdlin
> Cc: Hubert Feurstein
> Cc: Lukasz Majewski
> Signed-off-by: Arnd Bergmann
> ---
> arch/arm/Kconfig | 2 ++
> arch/arm/mach-ep93xx/adssphere.c | 1 +
> arch/arm/mach-ep93xx/edb93xx.c | 8
> arch/arm/mach-ep93xx/gesbc9312.c | 1 +
> arch/arm/mach-ep93xx/{include/mach => }/irqs.h | 7 ---
> arch/arm/mach-ep93xx/micro9.c | 4
> arch/arm/mach-ep93xx/simone.c | 1 +
> arch/arm/mach-ep93xx/snappercl15.c | 1 +
> arch/arm/mach-ep93xx/soc.h | 1 +
> arch/arm/mach-ep93xx/ts72xx.c | 3 ++-
> arch/arm/mach-ep93xx/vision_ep9307.c | 1 +
> 11 files changed, 22 insertions(+), 8 deletions(-)
> rename arch/arm/mach-ep93xx/{include/mach => }/irqs.h (94%)
--
Alexander Sverdlin.
[PATCH 2/6] ARM: ep93xx: enable SPARSE_IRQ
Without CONFIG_SPARSE_IRQ, we rely on mach/irqs.h to define NR_IRQS
globally. Do the minimal conversion by setting .nr_irqs in each
machine descriptor.
Only the vision_ep9307 machine has extra IRQs for GPIOs, so make
.nr_irqs the original value there, while using the plain NR_EP93XX_IRQS
everywhere else.
---
It's been a while since I did this, no idea what else is needed
here or if this is correct at all.
Cc: Hartley Sweeten
Cc: Alexander Sverdlin
Cc: Hubert Feurstein
Cc: Lukasz Majewski
Signed-off-by: Arnd Bergmann
---
arch/arm/Kconfig | 2 ++
arch/arm/mach-ep93xx/adssphere.c | 1 +
arch/arm/mach-ep93xx/edb93xx.c | 8
arch/arm/mach-ep93xx/gesbc9312.c | 1 +
arch/arm/mach-ep93xx/{include/mach => }/irqs.h | 7 ---
arch/arm/mach-ep93xx/micro9.c | 4
arch/arm/mach-ep93xx/simone.c | 1 +
arch/arm/mach-ep93xx/snappercl15.c | 1 +
arch/arm/mach-ep93xx/soc.h | 1 +
arch/arm/mach-ep93xx/ts72xx.c | 3 ++-
arch/arm/mach-ep93xx/vision_ep9307.c | 1 +
11 files changed, 22 insertions(+), 8 deletions(-)
rename arch/arm/mach-ep93xx/{include/mach => }/irqs.h (94%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b6681b61e46c..cca3d240a01e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -365,6 +365,8 @@ config ARCH_EP93XX
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select GPIOLIB
+ select IRQ_DOMAIN
+ select SPARSE_IRQ
help
This enables support for the Cirrus EP93xx series of CPUs.
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 57cfd8ebe04f..bb5e7b3c2fba 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -32,6 +32,7 @@ static void __init adssphere_init_machine(void)
MACHINE_START(ADSSPHERE, "ADS Sphere board")
/* Maintainer: Lennert Buytenhek */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 7b7280c21ee0..19f38f58ff46 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -243,6 +243,7 @@ static void __init edb93xx_init_machine(void)
MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
/* Maintainer: H Hartley Sweeten */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -256,6 +257,7 @@ MACHINE_END
MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
/* Maintainer: George Kashperko */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -269,6 +271,7 @@ MACHINE_END
MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
/* Maintainer: Lennert Buytenhek */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -282,6 +285,7 @@ MACHINE_END
MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
/* Maintainer: Herbert Valerio Riedel */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -295,6 +299,7 @@ MACHINE_END
MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
/* Maintainer: H Hartley Sweeten */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -308,6 +313,7 @@ MACHINE_END
MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
/* Maintainer: Toufeeq Hussain */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -321,6 +327,7 @@ MACHINE_END
MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
/* Maintainer: Lennert Buytenhek */
.atag_offset= 0x100,
+ .nr_irqs= NR_EP93XX_IRQS,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
.init_time = ep93xx_timer_init,
@@ -334,6 +341,7 @@ MACHINE_END
MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
/* Maintainer: Lennert
