Hi,
On 21/12/2018 07:27, Andrey Smirnov wrote:
> Convert various mult-bit fields to be defined using
> GENMASK/FIELD_PREP. This way bit field boundaries are defined in a
> single place only as well as defined in a way that makes it easier to
> verify them against reference manual. No functional change intended.
>
> Cc: Lorenzo Pieralisi
> Cc: Bjorn Helgaas
> Cc: Fabio Estevam
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Leonard Crestez
> Cc: "A.s. Dong"
> Cc: Richard Zhu
> Cc: linux-...@nxp.com
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Andrey Smirnov
> ---
> drivers/pci/controller/dwc/pcie-designware.h | 29 +++-
> 1 file changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> b/drivers/pci/controller/dwc/pcie-designware.h
> index 348e91b6daa2..0de653284fca 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -11,6 +11,7 @@
> #ifndef _PCIE_DESIGNWARE_H
> #define _PCIE_DESIGNWARE_H
>
> +#include
> #include
> #include
> #include
> @@ -30,11 +31,12 @@
>
> /* Synopsys-specific PCIe configuration registers */
> #define PCIE_PORT_LINK_CONTROL 0x710
> -#define PORT_LINK_MODE_MASK (0x3f << 16)
> -#define PORT_LINK_MODE_1_LANES (0x1 << 16)
> -#define PORT_LINK_MODE_2_LANES (0x3 << 16)
> -#define PORT_LINK_MODE_4_LANES (0x7 << 16)
> -#define PORT_LINK_MODE_8_LANES (0xf << 16)
> +#define PORT_LINK_MODE_MASK GENMASK(21, 16)
> +#define PORT_LINK_MODE(n)FIELD_PREP(PORT_LINK_MODE_MASK, n)
> +#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
> +#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
> +#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
> +#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
>
> #define PCIE_PORT_DEBUG0 0x728
> #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
> @@ -45,11 +47,12 @@
>
> #define PCIE_LINK_WIDTH_SPEED_CONTROL0x80C
> #define PORT_LOGIC_SPEED_CHANGE BIT(17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
> -#define PORT_LOGIC_LINK_WIDTH_1_LANES(0x1 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_2_LANES(0x2 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_4_LANES(0x4 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_8_LANES(0x8 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
> +#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK,
> n)
> +#define PORT_LOGIC_LINK_WIDTH_1_LANESPORT_LOGIC_LINK_WIDTH(0x1)
> +#define PORT_LOGIC_LINK_WIDTH_2_LANESPORT_LOGIC_LINK_WIDTH(0x2)
> +#define PORT_LOGIC_LINK_WIDTH_4_LANESPORT_LOGIC_LINK_WIDTH(0x4)
> +#define PORT_LOGIC_LINK_WIDTH_8_LANESPORT_LOGIC_LINK_WIDTH(0x8)
>
> #define PCIE_MSI_ADDR_LO 0x820
> #define PCIE_MSI_ADDR_HI 0x824
> @@ -75,9 +78,9 @@
> #define PCIE_ATU_UPPER_BASE 0x910
> #define PCIE_ATU_LIMIT 0x914
> #define PCIE_ATU_LOWER_TARGET0x918
> -#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
> -#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
> -#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> +#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
> +#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
> +#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
> #define PCIE_ATU_UPPER_TARGET0x91C
>
> #define PCIE_MISC_CONTROL_1_OFF 0x8BC
>
I wasn't aware of the existence of FIELD_PREP(), seems to be quite handy :)
Acked-by: Gustavo Pimentel
Thanks.
