Re: [PATCH 3/4] powerpc: pm: add EPU FSM configuration for deep sleep
On Mon, 2015-08-03 at 20:01 +0800, Chenhui Zhao wrote: > On Sat, Aug 1, 2015 at 8:41 AM, Scott Wood > wrote: > > On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote: > > > In the last stage of deep sleep, software will trigger a Finite > > > State Machine (FSM) to control the hardware precedure, such as > > > board isolation, killing PLLs, removing power, and so on. > > > > > > When the system is waked up by an interrupt, the FSM controls the > > > hardware to complete the early resume precedure. > > > > > > This patch configure the EPU FSM preparing for deep sleep. > > > > > > Signed-off-by: Chenhui Zhao > > > --- > > > arch/powerpc/platforms/85xx/Makefile| 2 +- > > > arch/powerpc/platforms/85xx/sleep_fsm.c | 256 > > > > > > arch/powerpc/platforms/85xx/sleep_fsm.h | 104 + > > > 3 files changed, 361 insertions(+), 1 deletion(-) > > > create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.c > > > create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.h > > > > When I asked why this was in drivers/platform[1], you said it was to > > share > > with LS1, and that the values used were the same -- so why did you > > move it to > > arch/powerpc? > > There are some changes. LS1 will use PSCI (Power State Coordination > Interface) to implement deep sleep. So these code just used by PowerPC. Then remove the comment about the values being usable on ls1021. -Scott -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/4] powerpc: pm: add EPU FSM configuration for deep sleep
On Sat, Aug 1, 2015 at 8:41 AM, Scott Wood
wrote:
On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote:
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls the
hardware to complete the early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 256
arch/powerpc/platforms/85xx/sleep_fsm.h | 104 +
3 files changed, 361 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.c
create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.h
When I asked why this was in drivers/platform[1], you said it was to
share
with LS1, and that the values used were the same -- so why did you
move it to
arch/powerpc?
There are some changes. LS1 will use PSCI (Power State Coordination
Interface) to implement deep sleep. So these code just used by PowerPC.
[1] Note that other proposed patches create a drivers/soc/fsl instead
of
drivers/platform/fsl... We need one of them, not both.
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
+{
+ struct fsm_reg_vals *data = val;
+
+ BUG_ON(!base || !data);
This BUG_ON is useless. If one of those is NULL you'll get an oops
anyway.
diff --git a/arch/powerpc/platforms/85xx/sleep_fsm.h
b/arch/powerpc/platforms/85xx/sleep_fsm.h
new file mode 100644
index 000..2c60b40
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/sleep_fsm.h
@@ -0,0 +1,104 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2015 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+#ifndef _FSL_SLEEP_FSM_H
+#define _FSL_SLEEP_FSM_H
+
+#define FSL_STRIDE_4B4
+#define FSL_STRIDE_8B8
Why not just use 4/8 directly?
+/* Block offsets */
+#define RCPM_BLOCK_OFFSET0x00022000
+#define EPU_BLOCK_OFFSET 0x
+#define NPC_BLOCK_OFFSET 0x1000
I thought you said OK to not putting these offsets in the kernel
source...
-Scott
OK. Will change them.
-Chenhui
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Re: [PATCH 3/4] powerpc: pm: add EPU FSM configuration for deep sleep
On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote:
> In the last stage of deep sleep, software will trigger a Finite
> State Machine (FSM) to control the hardware precedure, such as
> board isolation, killing PLLs, removing power, and so on.
>
> When the system is waked up by an interrupt, the FSM controls the
> hardware to complete the early resume precedure.
>
> This patch configure the EPU FSM preparing for deep sleep.
>
> Signed-off-by: Chenhui Zhao
> ---
> arch/powerpc/platforms/85xx/Makefile| 2 +-
> arch/powerpc/platforms/85xx/sleep_fsm.c | 256
>
> arch/powerpc/platforms/85xx/sleep_fsm.h | 104 +
> 3 files changed, 361 insertions(+), 1 deletion(-)
> create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.c
> create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.h
When I asked why this was in drivers/platform[1], you said it was to share
with LS1, and that the values used were the same -- so why did you move it to
arch/powerpc?
[1] Note that other proposed patches create a drivers/soc/fsl instead of
drivers/platform/fsl... We need one of them, not both.
> +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
> +{
> + struct fsm_reg_vals *data = val;
> +
> + BUG_ON(!base || !data);
This BUG_ON is useless. If one of those is NULL you'll get an oops anyway.
> diff --git a/arch/powerpc/platforms/85xx/sleep_fsm.h
> b/arch/powerpc/platforms/85xx/sleep_fsm.h
> new file mode 100644
> index 000..2c60b40
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/sleep_fsm.h
> @@ -0,0 +1,104 @@
> +/*
> + * Freescale deep sleep FSM (finite-state machine) configuration
> + *
> + * Copyright 2015 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#ifndef _FSL_SLEEP_FSM_H
> +#define _FSL_SLEEP_FSM_H
> +
> +#define FSL_STRIDE_4B4
> +#define FSL_STRIDE_8B8
Why not just use 4/8 directly?
>
> +/* Block offsets */
> +#define RCPM_BLOCK_OFFSET0x00022000
> +#define EPU_BLOCK_OFFSET 0x
> +#define NPC_BLOCK_OFFSET 0x1000
I thought you said OK to not putting these offsets in the kernel source...
-Scott
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/4] powerpc: pm: add EPU FSM configuration for deep sleep
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls the
hardware to complete the early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 256
arch/powerpc/platforms/85xx/sleep_fsm.h | 104 +
3 files changed, 361 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.c
create mode 100644 arch/powerpc/platforms/85xx/sleep_fsm.h
diff --git a/arch/powerpc/platforms/85xx/Makefile
b/arch/powerpc/platforms/85xx/Makefile
index fdae28b..87fb847 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -3,7 +3,7 @@
#
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_FSL_PMC)+= mpc85xx_pm_ops.o
-obj-$(CONFIG_FSL_QORIQ_PM) += qoriq_pm.o
+obj-$(CONFIG_FSL_QORIQ_PM) += qoriq_pm.o sleep_fsm.o
obj-y += common.o
diff --git a/arch/powerpc/platforms/85xx/sleep_fsm.c
b/arch/powerpc/platforms/85xx/sleep_fsm.c
new file mode 100644
index 000..2e81d37
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/sleep_fsm.c
@@ -0,0 +1,256 @@
+/*
+ * Freescale deep sleep FSM (finite-state machine) configuration
+ *
+ * Copyright 2015 Freescale Semiconductor Inc.
+ *
+ * Author: Hongbo Zhang
+ * Chenhui Zhao
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+
+#include "sleep_fsm.h"
+/*
+ * These values are from chip's reference manual. For example,
+ * the values for T1040 can be found in "8.4.3.8 Programming
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
+ * Power Management (RCPM)".
+ * The default value can be applied to T104x, LS1021.
+ */
+struct fsm_reg_vals epu_default_val[] = {
+ /* EPGCR (Event Processor Global Control Register) */
+ {EPGCR, 0},
+ /* EPECR (Event Processor Event Control Registers) */
+ {EPECR0 + EPECR_STRIDE * 0, 0},
+ {EPECR0 + EPECR_STRIDE * 1, 0},
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
+ {EPECR0 + EPECR_STRIDE * 3, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 4, 0x2084},
+ {EPECR0 + EPECR_STRIDE * 5, 0x0804},
+ {EPECR0 + EPECR_STRIDE * 6, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 7, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 8, 0x6084},
+ {EPECR0 + EPECR_STRIDE * 9, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 10, 0x4284},
+ {EPECR0 + EPECR_STRIDE * 11, 0x9084},
+ {EPECR0 + EPECR_STRIDE * 12, 0x8084},
+ {EPECR0 + EPECR_STRIDE * 13, 0x0884},
+ {EPECR0 + EPECR_STRIDE * 14, 0x0284},
+ {EPECR0 + EPECR_STRIDE * 15, 0x0004},
+ /*
+* EPEVTCR (Event Processor EVT Pin Control Registers)
+* SCU8 triger EVT2, and SCU11 triger EVT9
+*/
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x8001},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB001},
+ /* EPCMPR (Event Processor Counter Compare Registers) */
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x0020},
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x00FF},
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x00FF},
+ /* EPCCR (Event Processor Counter Control Registers) */
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x9284},
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x9284},
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x9284},
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
+ {EPCCR0 + EPCCR_STRIDE * 7,
