Re: [PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-14 Thread yixin zhu 




On 6/12/2018 7:23 PM, James Hogan wrote:

Hi,

Good to see this patch!

On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index ac7ad54f984f..bcd647060f3e 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -12,6 +12,7 @@ platforms += cobalt
  platforms += dec
  platforms += emma
  platforms += generic
+platforms += intel-mips


What are the main things preventing this from moving to the generic
platform? Is it mainly the use of EVA (which generic doesn't yet
support)?


Yes. It's mainly because of EVA.


diff --git a/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h 
b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h
new file mode 100644
index ..3893855b60c6
--- /dev/null
+++ b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h

...

+   /*
+* Get Config.K0 value and use it to program
+* the segmentation registers


Please can you describe (maybe with a table) the segment layout in human
readable terms so the reader doesn't need to decode the SegCtl registers
to understand where everything is in the virtual address space?


Will add detailed EVA mapping description in code comments.


diff --git a/arch/mips/boot/dts/intel-mips/Makefile 
b/arch/mips/boot/dts/intel-mips/Makefile
new file mode 100644
index ..b16c0081639c
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_INTEL_MIPS_GRX500)+= easy350_anywan.dtb
+obj-y  += $(patsubst %.dtb, %.dtb.o, $(dtb-y))


This needs updating to obj-$(CONFIG_BUILTIN_DTB) as per commit
fca3aa166422 ("MIPS: dts: Avoid unneeded built-in.a in DTS dirs") in
linux-next.


diff --git a/arch/mips/intel-mips/Makefile b/arch/mips/intel-mips/Makefile
new file mode 100644
index ..9f272d06eecd
--- /dev/null
+++ b/arch/mips/intel-mips/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTEL_MIPS)   += prom.o irq.o time.o


You can use obj-y, since this Makefile is only included if
CONFIG_INTEL_MIPS=y (i.e. via the platform-$(CONFIG_INTEL_MIPS) below).

Also please split each file onto separate "obj-y += whatever.o" lines.


Will use obj-y.
Will split it into per line per .o.


diff --git a/arch/mips/intel-mips/Platform b/arch/mips/intel-mips/Platform
new file mode 100644
index ..b34750eeaeb0
--- /dev/null
+++ b/arch/mips/intel-mips/Platform
@@ -0,0 +1,11 @@
+#
+# MIPs SoC platform
+#
+
+platform-$(CONFIG_INTEL_MIPS)  += intel-mips/


^^^ (this is what ensures the Makefile is only included for this
platform)


diff --git a/arch/mips/intel-mips/irq.c b/arch/mips/intel-mips/irq.c
new file mode 100644
index ..00637a5cdd20
--- /dev/null
+++ b/arch/mips/intel-mips/irq.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+void __init arch_init_irq(void)
+{
+   struct device_node *intc_node;
+
+   pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off");
+   pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off");
+
+   intc_node = of_find_compatible_node(NULL, NULL,
+   "mti,cpu-interrupt-controller");
+   if (!cpu_has_veic && !intc_node)
+   mips_cpu_irq_init();
+
+   irqchip_init();
+}
+
+int get_c0_perfcount_int(void)
+{
+   return gic_get_c0_perfcount_int();
+}
+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
+
+unsigned int get_c0_compare_int(void)
+{
+   return gic_get_c0_compare_int();
+}


Worth having get_c0_fdc_int() too for the "Fast Debug Channel"?


FDC not used in our product.


diff --git a/arch/mips/intel-mips/prom.c b/arch/mips/intel-mips/prom.c
new file mode 100644
index ..9407858ddc94
--- /dev/null
+++ b/arch/mips/intel-mips/prom.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014 Lei Chuanhua 
+ * Copyright (C) 2016 Intel Corporation.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define IOPORT_RESOURCE_START   0x1000
+#define IOPORT_RESOURCE_END 0x
+#define IOMEM_RESOURCE_START0x1000
+#define IOMEM_RESOURCE_END  0x


The _END ones seem to be unused?


Will remove unused _END macros.


+static void __init prom_init_cmdline(void)
+{
+   int i;
+   int argc;
+   char **argv;
+
+   /*
+* If u-boot pass parameters, it is ok, however, if without u-boot
+* JTAG or other tool has to reset all register value before it goes
+* emulation most likely belongs to this category
+*/
+   if (fw_arg0 == 0 || fw_arg1 == 0)
+   return;
+
+   argc = fw_arg0;
+   argv = (char **)KSEG1ADDR(fw_arg1);
+
+   arcs_cmdline[0] = '\0';
+
+   for (i = 0; i < argc

Re: [PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-14 Thread Hua Ma 



On 6/13/2018 6:31 AM, Rob Herring wrote:

On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:

From: Hua Ma 

Add initial support for Intel MIPS interAptiv SoCs made by Intel.
This series will add support for the GRX500 family.

The series allows booting a minimal system using a initramfs.

Signed-off-by: Hua ma 
Signed-off-by: Songjun Wu 
---

  arch/mips/Kbuild.platforms |   1 +
  arch/mips/Kconfig  |  36 
  arch/mips/boot/dts/Makefile|   1 +
  arch/mips/boot/dts/intel-mips/Makefile |   3 +
  arch/mips/boot/dts/intel-mips/easy350_anywan.dts   |  20 +++
  arch/mips/boot/dts/intel-mips/xrx500.dtsi  | 196 +

Please split dts files to separate patch.

Thanks,
it will be split into separate patches: one for dts, one for mips codes 
and one for the document.

diff --git a/arch/mips/boot/dts/intel-mips/easy350_anywan.dts 
b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
new file mode 100644
index ..40177f6cee1e
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include 
+#include 
+
+#include "xrx500.dtsi"
+
+/ {
+   model = "EASY350 ANYWAN (GRX350) Main model";

A board should have a board specific compatible, too.

The board compatible will be added.



+   chosen {
+   bootargs = "earlycon=lantiq,0x1660 clk_ignore_unused";
+   stdout-path = "serial0";
+   };
+
+   memory@0 {

memory@2000

The memory address will be changed to @2000.



+   device_type = "memory";
+   reg = <0x2000 0x0e00>;
+   };
+};
diff --git a/arch/mips/boot/dts/intel-mips/xrx500.dtsi 
b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
new file mode 100644
index ..04a068d6d96b
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "intel,xrx500";

This needs to be documented.

The compatible will be updated in the document.

Re: [PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-12 Thread Rob Herring 
On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:
> From: Hua Ma 
> 
> Add initial support for Intel MIPS interAptiv SoCs made by Intel.
> This series will add support for the GRX500 family.
> 
> The series allows booting a minimal system using a initramfs.
> 
> Signed-off-by: Hua ma 
> Signed-off-by: Songjun Wu 
> ---
> 
>  arch/mips/Kbuild.platforms |   1 +
>  arch/mips/Kconfig  |  36 
>  arch/mips/boot/dts/Makefile|   1 +
>  arch/mips/boot/dts/intel-mips/Makefile |   3 +
>  arch/mips/boot/dts/intel-mips/easy350_anywan.dts   |  20 +++
>  arch/mips/boot/dts/intel-mips/xrx500.dtsi  | 196 
> +

Please split dts files to separate patch.


> diff --git a/arch/mips/boot/dts/intel-mips/easy350_anywan.dts 
> b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
> new file mode 100644
> index ..40177f6cee1e
> --- /dev/null
> +++ b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include 
> +#include 
> +
> +#include "xrx500.dtsi"
> +
> +/ {
> + model = "EASY350 ANYWAN (GRX350) Main model";

A board should have a board specific compatible, too. 

> + chosen {
> + bootargs = "earlycon=lantiq,0x1660 clk_ignore_unused";
> + stdout-path = "serial0";
> + };
> +
> + memory@0 {

memory@2000

> + device_type = "memory";
> + reg = <0x2000 0x0e00>;
> + };
> +};
> diff --git a/arch/mips/boot/dts/intel-mips/xrx500.dtsi 
> b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
> new file mode 100644
> index ..04a068d6d96b
> --- /dev/null
> +++ b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "intel,xrx500";

This needs to be documented.

> +
> + aliases {
> + serial0 = &asc0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "mti,interaptiv";
> + clocks = <&cpuclk>;
> + reg = <0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "mti,interaptiv";
> + reg = <1>;
> + };
> + };
> +
> + cpu_intc: interrupt-controller {
> + compatible = "mti,cpu-interrupt-controller";
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + gic: gic@1232 {
> + compatible = "mti,gic";
> + reg = <0x1232 0x2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + /*
> +  * Declare the interrupt-parent even though the mti,gic
> +  * binding doesn't require it, such that the kernel can
> +  * figure out that cpu_intc is the root interrupt
> +  * controller & should be probed first.
> +  */
> + interrupt-parent = <&cpu_intc>;
> + mti,reserved-ipi-vectors = <56 8>;
> + };
> +
> + cgu0: cgu@1620 {
> + compatible = "syscon";
> + reg = <0x1620 0x10>;
> +
> + clock {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + osc0: osc0 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <4000>;
> + clock-output-names = "osc40M";
> + };
> +
> + pll0a: pll0a {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-mult = <0x3C>;
> + clock-div = <1>;
> + clocks = <&osc0>;
> + clock-output-names = "pll0a";
> + };
> +
> + pll0b: pll0b {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-mult = <0x32>;
> + clock-div = <1>;
> + clocks = <&osc0>;
> + clock-output-names = "pll0b";
> + };
> +
> + pll3: pll3 {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clock-mult = <0x64>;
> + clock-div = <1>

Re: [PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-12 Thread James Hogan 
Hi,

Good to see this patch!

On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index ac7ad54f984f..bcd647060f3e 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -12,6 +12,7 @@ platforms += cobalt
>  platforms += dec
>  platforms += emma
>  platforms += generic
> +platforms += intel-mips

What are the main things preventing this from moving to the generic
platform? Is it mainly the use of EVA (which generic doesn't yet
support)?

> diff --git a/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h 
> b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h
> new file mode 100644
> index ..3893855b60c6
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h
...
> + /*
> +  * Get Config.K0 value and use it to program
> +  * the segmentation registers

Please can you describe (maybe with a table) the segment layout in human
readable terms so the reader doesn't need to decode the SegCtl registers
to understand where everything is in the virtual address space?

> diff --git a/arch/mips/boot/dts/intel-mips/Makefile 
> b/arch/mips/boot/dts/intel-mips/Makefile
> new file mode 100644
> index ..b16c0081639c
> --- /dev/null
> +++ b/arch/mips/boot/dts/intel-mips/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_DTB_INTEL_MIPS_GRX500)  += easy350_anywan.dtb
> +obj-y+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))

This needs updating to obj-$(CONFIG_BUILTIN_DTB) as per commit
fca3aa166422 ("MIPS: dts: Avoid unneeded built-in.a in DTS dirs") in
linux-next.

> diff --git a/arch/mips/intel-mips/Makefile b/arch/mips/intel-mips/Makefile
> new file mode 100644
> index ..9f272d06eecd
> --- /dev/null
> +++ b/arch/mips/intel-mips/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_INTEL_MIPS) += prom.o irq.o time.o

You can use obj-y, since this Makefile is only included if
CONFIG_INTEL_MIPS=y (i.e. via the platform-$(CONFIG_INTEL_MIPS) below).

Also please split each file onto separate "obj-y += whatever.o" lines.

> diff --git a/arch/mips/intel-mips/Platform b/arch/mips/intel-mips/Platform
> new file mode 100644
> index ..b34750eeaeb0
> --- /dev/null
> +++ b/arch/mips/intel-mips/Platform
> @@ -0,0 +1,11 @@
> +#
> +# MIPs SoC platform
> +#
> +
> +platform-$(CONFIG_INTEL_MIPS)+= intel-mips/

^^^ (this is what ensures the Makefile is only included for this
platform)

> diff --git a/arch/mips/intel-mips/irq.c b/arch/mips/intel-mips/irq.c
> new file mode 100644
> index ..00637a5cdd20
> --- /dev/null
> +++ b/arch/mips/intel-mips/irq.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016 Intel Corporation.
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +void __init arch_init_irq(void)
> +{
> + struct device_node *intc_node;
> +
> + pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off");
> + pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off");
> +
> + intc_node = of_find_compatible_node(NULL, NULL,
> + "mti,cpu-interrupt-controller");
> + if (!cpu_has_veic && !intc_node)
> + mips_cpu_irq_init();
> +
> + irqchip_init();
> +}
> +
> +int get_c0_perfcount_int(void)
> +{
> + return gic_get_c0_perfcount_int();
> +}
> +EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
> +
> +unsigned int get_c0_compare_int(void)
> +{
> + return gic_get_c0_compare_int();
> +}

Worth having get_c0_fdc_int() too for the "Fast Debug Channel"?

> diff --git a/arch/mips/intel-mips/prom.c b/arch/mips/intel-mips/prom.c
> new file mode 100644
> index ..9407858ddc94
> --- /dev/null
> +++ b/arch/mips/intel-mips/prom.c
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2014 Lei Chuanhua 
> + * Copyright (C) 2016 Intel Corporation.
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define IOPORT_RESOURCE_START   0x1000
> +#define IOPORT_RESOURCE_END 0x
> +#define IOMEM_RESOURCE_START0x1000
> +#define IOMEM_RESOURCE_END  0x

The _END ones seem to be unused?

> +static void __init prom_init_cmdline(void)
> +{
> + int i;
> + int argc;
> + char **argv;
> +
> + /*
> +  * If u-boot pass parameters, it is ok, however, if without u-boot
> +  * JTAG or other tool has to reset all register value before it goes
> +  * emulation most likely belongs to this category
> +  */
> + if (fw_arg0 == 0 || fw_arg1 == 0)
> + return;
> +
> + argc = fw_arg0;
> + argv = (char **)KSEG1ADDR(fw_arg1);
> +
> + arcs_cmdline[0] = '\0';
> +
> + for (i = 0; i < argc; i++) {
> + char *p = (char *)KSEG1ADDR(arg

[PATCH 3/7] MIPS: intel: Add initial support for Intel MIPS SoCs

2018-06-11 Thread Songjun Wu 
From: Hua Ma 

Add initial support for Intel MIPS interAptiv SoCs made by Intel.
This series will add support for the GRX500 family.

The series allows booting a minimal system using a initramfs.

Signed-off-by: Hua ma 
Signed-off-by: Songjun Wu 
---

 arch/mips/Kbuild.platforms |   1 +
 arch/mips/Kconfig  |  36 
 arch/mips/boot/dts/Makefile|   1 +
 arch/mips/boot/dts/intel-mips/Makefile |   3 +
 arch/mips/boot/dts/intel-mips/easy350_anywan.dts   |  20 +++
 arch/mips/boot/dts/intel-mips/xrx500.dtsi  | 196 +
 arch/mips/configs/grx500_defconfig | 165 +
 .../asm/mach-intel-mips/cpu-feature-overrides.h|  61 +++
 arch/mips/include/asm/mach-intel-mips/ioremap.h|  39 
 arch/mips/include/asm/mach-intel-mips/irq.h|  17 ++
 .../asm/mach-intel-mips/kernel-entry-init.h|  76 
 arch/mips/include/asm/mach-intel-mips/spaces.h |  29 +++
 arch/mips/include/asm/mach-intel-mips/war.h|  18 ++
 arch/mips/intel-mips/Kconfig   |  22 +++
 arch/mips/intel-mips/Makefile  |   3 +
 arch/mips/intel-mips/Platform  |  11 ++
 arch/mips/intel-mips/irq.c |  36 
 arch/mips/intel-mips/prom.c| 184 +++
 arch/mips/intel-mips/time.c|  56 ++
 19 files changed, 974 insertions(+)
 create mode 100644 arch/mips/boot/dts/intel-mips/Makefile
 create mode 100644 arch/mips/boot/dts/intel-mips/easy350_anywan.dts
 create mode 100644 arch/mips/boot/dts/intel-mips/xrx500.dtsi
 create mode 100644 arch/mips/configs/grx500_defconfig
 create mode 100644 
arch/mips/include/asm/mach-intel-mips/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-intel-mips/ioremap.h
 create mode 100644 arch/mips/include/asm/mach-intel-mips/irq.h
 create mode 100644 arch/mips/include/asm/mach-intel-mips/kernel-entry-init.h
 create mode 100644 arch/mips/include/asm/mach-intel-mips/spaces.h
 create mode 100644 arch/mips/include/asm/mach-intel-mips/war.h
 create mode 100644 arch/mips/intel-mips/Kconfig
 create mode 100644 arch/mips/intel-mips/Makefile
 create mode 100644 arch/mips/intel-mips/Platform
 create mode 100644 arch/mips/intel-mips/irq.c
 create mode 100644 arch/mips/intel-mips/prom.c
 create mode 100644 arch/mips/intel-mips/time.c

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index ac7ad54f984f..bcd647060f3e 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -12,6 +12,7 @@ platforms += cobalt
 platforms += dec
 platforms += emma
 platforms += generic
+platforms += intel-mips
 platforms += jazz
 platforms += jz4740
 platforms += lantiq
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 225c95da23ce..c82cebeb6192 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -404,6 +404,41 @@ config LANTIQ
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER
 
+config INTEL_MIPS
+   bool "Intel MIPS interAptiv SoC based platforms"
+   select ARCH_HAS_RESET_CONTROLLER
+   select ARCH_SUPPORTS_MSI
+   select BOOT_RAW
+   select CEVT_R4K
+   select COMMON_CLK
+   select CPU_MIPS32_3_5_EVA
+   select CPU_MIPS32_3_5_FEATURES
+   select CPU_MIPSR2_IRQ_EI
+   select CPU_MIPSR2_IRQ_VI
+   select CSRC_R4K
+   select DMA_NONCOHERENT
+   select GENERIC_ISA_DMA
+   select GPIOLIB
+   select HW_HAS_PCI
+   select IRQ_MIPS_CPU
+   select MFD_CORE
+   select MFD_SYSCON
+   select MIPS_CPU_SCACHE
+   select MIPS_GIC
+   select PCI_DRIVERS_GENERIC
+   select RESET_CONTROLLER
+   select SYS_HAS_CPU_MIPS32_R1
+   select SYS_HAS_CPU_MIPS32_R2
+   select SYS_HAS_CPU_MIPS32_R3_5
+   select SYS_HAS_EARLY_PRINTK
+   select SYS_SUPPORTS_BIG_ENDIAN
+   select SYS_SUPPORTS_32BIT_KERNEL
+   select SYS_SUPPORTS_MIPS_CPS
+   select SYS_SUPPORTS_MULTITHREADING
+   select SYS_SUPPORTS_ZBOOT
+   select TIMER_OF
+   select USE_OF
+
 config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
@@ -1010,6 +1045,7 @@ source "arch/mips/bcm47xx/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/bmips/Kconfig"
 source "arch/mips/generic/Kconfig"
+source "arch/mips/intel-mips/Kconfig"
 source "arch/mips/jazz/Kconfig"
 source "arch/mips/jz4740/Kconfig"
 source "arch/mips/lantiq/Kconfig"
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..05f52f279047 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -3,6 +3,7 @@ subdir-y+= brcm
 subdir-y   += cavium-octeon
 subdir-y   += img
 subdir-y   += ingenic
+subdir-y   += intel-mips
 subdir-y   += lantiq
 subdir-y   += mscc
 subdir-y   += mti
diff --git a/arch/mips/boot/dts/in