[PATCH 4.8 24/35] drm/amdgpu: fix check for port PM availability

[Greg Kroah-Hartman]

4.8-stable review patch.  If anyone has any objections, please let me know.

--

From: Peter Wu 

commit 7ac33e47d5769632010e537964c7e45498f8dc26 upstream.

The ATPX method does not always exist on the dGPU, it may be located at
the iGPU. The parent device of the iGPU is the root port for which
bridge_d3 is false. This accidentally enables the legacy PM method which
conflicts with port PM and prevented the dGPU from powering on.

Fixes: 1db4496f167b ("drm/amdgpu: fix power state when port pm is unavailable")

Reported-and-tested-by: Mike Lothian 
Signed-off-by: Peter Wu 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c |   11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -476,7 +476,6 @@ static int amdgpu_atpx_power_state(enum
  */
 static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
 {
-   struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
acpi_handle dhandle, atpx_handle;
acpi_status status;
 
@@ -491,7 +490,6 @@ static bool amdgpu_atpx_pci_probe_handle
}
amdgpu_atpx_priv.dhandle = dhandle;
amdgpu_atpx_priv.atpx.handle = atpx_handle;
-   amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && 
parent_pdev->bridge_d3;
return true;
 }
 
@@ -553,17 +551,25 @@ static bool amdgpu_atpx_detect(void)
struct pci_dev *pdev = NULL;
bool has_atpx = false;
int vga_count = 0;
+   bool d3_supported = false;
+   struct pci_dev *parent_pdev;
 
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
vga_count++;
 
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+
+   parent_pdev = pci_upstream_bridge(pdev);
+   d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
 
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != 
NULL) {
vga_count++;
 
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+
+   parent_pdev = pci_upstream_bridge(pdev);
+   d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
 
if (has_atpx && vga_count == 2) {
@@ -571,6 +577,7 @@ static bool amdgpu_atpx_detect(void)
printk(KERN_INFO "vga_switcheroo: detected switching method %s 
handle\n",
   acpi_method_name);
amdgpu_atpx_priv.atpx_detected = true;
+   amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
amdgpu_atpx_init();
return true;
}

[PATCH 4.8 24/35] drm/amdgpu: fix check for port PM availability

[Greg Kroah-Hartman]

4.8-stable review patch.  If anyone has any objections, please let me know.

--

From: Peter Wu 

commit 7ac33e47d5769632010e537964c7e45498f8dc26 upstream.

The ATPX method does not always exist on the dGPU, it may be located at
the iGPU. The parent device of the iGPU is the root port for which
bridge_d3 is false. This accidentally enables the legacy PM method which
conflicts with port PM and prevented the dGPU from powering on.

Fixes: 1db4496f167b ("drm/amdgpu: fix power state when port pm is unavailable")

Reported-and-tested-by: Mike Lothian 
Signed-off-by: Peter Wu 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c |   11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -476,7 +476,6 @@ static int amdgpu_atpx_power_state(enum
  */
 static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
 {
-   struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
acpi_handle dhandle, atpx_handle;
acpi_status status;
 
@@ -491,7 +490,6 @@ static bool amdgpu_atpx_pci_probe_handle
}
amdgpu_atpx_priv.dhandle = dhandle;
amdgpu_atpx_priv.atpx.handle = atpx_handle;
-   amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && 
parent_pdev->bridge_d3;
return true;
 }
 
@@ -553,17 +551,25 @@ static bool amdgpu_atpx_detect(void)
struct pci_dev *pdev = NULL;
bool has_atpx = false;
int vga_count = 0;
+   bool d3_supported = false;
+   struct pci_dev *parent_pdev;
 
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
vga_count++;
 
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+
+   parent_pdev = pci_upstream_bridge(pdev);
+   d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
 
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != 
NULL) {
vga_count++;
 
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+
+   parent_pdev = pci_upstream_bridge(pdev);
+   d3_supported |= parent_pdev && parent_pdev->bridge_d3;
}
 
if (has_atpx && vga_count == 2) {
@@ -571,6 +577,7 @@ static bool amdgpu_atpx_detect(void)
printk(KERN_INFO "vga_switcheroo: detected switching method %s 
handle\n",
   acpi_method_name);
amdgpu_atpx_priv.atpx_detected = true;
+   amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
amdgpu_atpx_init();
return true;
}