[PATCH 4.8 35/96] drm/amdgpu: fix init save/restore list in gfx_v8.0

[Greg Kroah-Hartman]

4.8-stable review patch.  If anyone has any objections, please let me know.

--

From: Rex Zhu 

commit 202e0b227b906cb80a2791f21216a55d9468d61b upstream.

set valid data to mmRLC_SRM_INDEX_CNTL_ADDRx/DATAx.

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3798,8 +3798,12 @@ static int gfx_v8_0_init_save_restore_li
temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
data = mmRLC_SRM_INDEX_CNTL_DATA_0;
for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-   amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3, 
false);
-   amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
+   if (unique_indices[i] != 0) {
+   amdgpu_mm_wreg(adev, temp + i,
+   unique_indices[i] & 0x3, false);
+   amdgpu_mm_wreg(adev, data + i,
+   unique_indices[i] >> 20, false);
+   }
}
kfree(register_list_format);
 

[PATCH 4.8 35/96] drm/amdgpu: fix init save/restore list in gfx_v8.0

[Greg Kroah-Hartman]

4.8-stable review patch.  If anyone has any objections, please let me know.

--

From: Rex Zhu 

commit 202e0b227b906cb80a2791f21216a55d9468d61b upstream.

set valid data to mmRLC_SRM_INDEX_CNTL_ADDRx/DATAx.

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3798,8 +3798,12 @@ static int gfx_v8_0_init_save_restore_li
temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
data = mmRLC_SRM_INDEX_CNTL_DATA_0;
for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-   amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3, 
false);
-   amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
+   if (unique_indices[i] != 0) {
+   amdgpu_mm_wreg(adev, temp + i,
+   unique_indices[i] & 0x3, false);
+   amdgpu_mm_wreg(adev, data + i,
+   unique_indices[i] >> 20, false);
+   }
}
kfree(register_list_format);