[PATCH 4.9 004/116] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Greg Kroah-Hartman]

4.9-stable review patch.  If anyone has any objections, please let me know.

--

From: Andi Kleen 

commit b0c1ef52959582144bbea9a2b37db7f4c9e399f7 upstream.

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Signed-off-by: Andi Kleen 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-a...@firstfloor.org
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman 

---
 arch/x86/events/core.c   |8 ++--
 arch/x86/events/perf_event.h |2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   /*
+* When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+* LBR and BTS are still mutually exclusive.
+*/
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask;  /* LBR_SELECT valid bits */
const int   *lbr_sel_map;  /* lbr_select mappings */
boollbr_double_abort;  /* duplicated lbr aborts */
-   boollbr_pt_coexist;/* LBR may coexist with PT */
+   boollbr_pt_coexist;/* (LBR|BTS) may coexist 
with PT */
 
/*
 * Intel PT/LBR/BTS are exclusive

[PATCH 4.9 004/116] perf/x86: Fix exclusion of BTS and LBR for Goldmont

[Greg Kroah-Hartman]

4.9-stable review patch.  If anyone has any objections, please let me know.

--

From: Andi Kleen 

commit b0c1ef52959582144bbea9a2b37db7f4c9e399f7 upstream.

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Signed-off-by: Andi Kleen 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: alexander.shish...@intel.com
Cc: kan.li...@intel.com
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the 
core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-a...@firstfloor.org
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman 

---
 arch/x86/events/core.c   |8 ++--
 arch/x86/events/perf_event.h |2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
 {
int i;
 
-   if (x86_pmu.lbr_pt_coexist)
+   /*
+* When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+* LBR and BTS are still mutually exclusive.
+*/
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
 
if (!atomic_inc_not_zero(_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ fail_unlock:
 
 void x86_del_exclusive(unsigned int what)
 {
-   if (x86_pmu.lbr_pt_coexist)
+   if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
 
atomic_dec(_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask;  /* LBR_SELECT valid bits */
const int   *lbr_sel_map;  /* lbr_select mappings */
boollbr_double_abort;  /* duplicated lbr aborts */
-   boollbr_pt_coexist;/* LBR may coexist with PT */
+   boollbr_pt_coexist;/* (LBR|BTS) may coexist 
with PT */
 
/*
 * Intel PT/LBR/BTS are exclusive