[PATCH 4.9 42/61] PCI: aardvark: Set PIO_ADDR_LS correctly in advk_pcie_rd_conf()

[Greg Kroah-Hartman]

4.9-stable review patch.  If anyone has any objections, please let me know.

--

From: Victor Gu 

commit 4fa3999ee672c54a5498ce98e20fe3fdf9c1cbb4 upstream.

When setting the PIO_ADDR_LS register during a configuration read, we
were properly passing the device number, function number and register
number, but not the bus number, causing issues when reading the
configuration of PCIe devices.

Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: 
Signed-off-by: Victor Gu 
Reviewed-by: Wilson Ding 
Reviewed-by: Nadav Haklai 
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni 
Signed-off-by: Lorenzo Pieralisi 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/pci/host/pci-aardvark.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -175,8 +175,6 @@
 #define PCIE_CONFIG_WR_TYPE0   0xa
 #define PCIE_CONFIG_WR_TYPE1   0xb
 
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev)  (dev << 4)
 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
 #define PCIE_CONF_FUNC(fun)(((fun) & 0x7)  << 12)
@@ -458,7 +456,7 @@ static int advk_pcie_rd_conf(struct pci_
advk_writel(pcie, reg, PIO_CTRL);
 
/* Program the address registers */
-   reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+   reg = PCIE_CONF_ADDR(bus->number, devfn, where);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
 

[PATCH 4.9 42/61] PCI: aardvark: Set PIO_ADDR_LS correctly in advk_pcie_rd_conf()

[Greg Kroah-Hartman]

4.9-stable review patch.  If anyone has any objections, please let me know.

--

From: Victor Gu 

commit 4fa3999ee672c54a5498ce98e20fe3fdf9c1cbb4 upstream.

When setting the PIO_ADDR_LS register during a configuration read, we
were properly passing the device number, function number and register
number, but not the bus number, causing issues when reading the
configuration of PCIe devices.

Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: 
Signed-off-by: Victor Gu 
Reviewed-by: Wilson Ding 
Reviewed-by: Nadav Haklai 
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni 
Signed-off-by: Lorenzo Pieralisi 
Signed-off-by: Greg Kroah-Hartman 

---
 drivers/pci/host/pci-aardvark.c |4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -175,8 +175,6 @@
 #define PCIE_CONFIG_WR_TYPE0   0xa
 #define PCIE_CONFIG_WR_TYPE1   0xb
 
-/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
-#define PCIE_BDF(dev)  (dev << 4)
 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
 #define PCIE_CONF_FUNC(fun)(((fun) & 0x7)  << 12)
@@ -458,7 +456,7 @@ static int advk_pcie_rd_conf(struct pci_
advk_writel(pcie, reg, PIO_CTRL);
 
/* Program the address registers */
-   reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+   reg = PCIE_CONF_ADDR(bus->number, devfn, where);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);