[PATCH 5/6] drm/rockchip: vop: add rk3036 vop support

2015-12-16 Thread Mark Yao 
RK3036 registers layout is quite difference with rk3288 layout,
The IC design with different framework, rk3036 vop is VOP LITE,
and rk3288 is VOP FULL.

RK3036 support two overlay plane and one hwc plane, max output
resolution is 1080p. it support IOMMU, and its IOMMU same as
rk3288's.

Signed-off-by: Mark Yao 
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  296 +--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  243 +-
 2 files changed, 336 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 6495114..3166b46 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -25,7 +25,7 @@
 .mask = _mask, \
 .shift = s,}
 
-static const uint32_t formats_01[] = {
+static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
DRM_FORMAT_ARGB,
DRM_FORMAT_XBGR,
@@ -39,7 +39,7 @@ static const uint32_t formats_01[] = {
DRM_FORMAT_NV24,
 };
 
-static const uint32_t formats_234[] = {
+static const uint32_t formats_win_lite[] = {
DRM_FORMAT_XRGB,
DRM_FORMAT_ARGB,
DRM_FORMAT_XBGR,
@@ -50,102 +50,103 @@ static const uint32_t formats_234[] = {
DRM_FORMAT_BGR565,
 };
 
-static const struct vop_scl_extension win_full_ext = {
-   .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
-   .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
-   .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
-   .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
-   .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
-   .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
-   .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
-   .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
-   .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
-   .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
-   .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
-   .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
-   .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
-   .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
-   .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
-   .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
-   .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
-   .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
-   .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
-   .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
-   .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
-};
-
-static const struct vop_scl_regs win_full_scl = {
-   .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0x, 0x0),
-   .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0x, 16),
-   .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0x, 0x0),
-   .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0x, 16),
-};
-
-static const struct vop_win_phy win01_data = {
-   .scl = _full_scl,
-   .data_formats = formats_01,
-   .nformats = ARRAY_SIZE(formats_01),
-   .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
-   .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
-   .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
-   .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
-   .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
-   .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
-   .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0x, 0),
-   .uv_mst = VOP_REG(WIN0_CBR_MST, 0x, 0),
-   .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
-   .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
-   .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
-   .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
-};
-
-static const struct vop_win_phy win23_data = {
-   .data_formats = formats_234,
-   .nformats = ARRAY_SIZE(formats_234),
-   .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
-   .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
-   .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
-   .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
-   .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
-   .yrgb_mst = VOP_REG(WIN2_MST0, 0x, 0),
-   .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
-   .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
-   .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
-};
-
-static const struct vop_ctrl ctrl_data = {
-   .standby = VOP_REG(SYS_CTRL, 0x1, 22),
-   .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
-   .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
-   .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
-   .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
-   .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
-   .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
-   .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
-   .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
-   .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
-   .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
-   .pin_pol = VOP_REG(DSP_CTRL0, 0xf,

[PATCH 5/6] drm/rockchip: vop: add rk3036 vop support

2015-12-16 Thread Mark Yao 
RK3036 registers layout is quite difference with rk3288 layout,
The IC design with different framework, rk3036 vop is VOP LITE,
and rk3288 is VOP FULL.

RK3036 support two overlay plane and one hwc plane, max output
resolution is 1080p. it support IOMMU, and its IOMMU same as
rk3288's.

Signed-off-by: Mark Yao 
---
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  296 +--
 drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  243 +-
 2 files changed, 336 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c 
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index 6495114..3166b46 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -25,7 +25,7 @@
 .mask = _mask, \
 .shift = s,}
 
-static const uint32_t formats_01[] = {
+static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB,
DRM_FORMAT_ARGB,
DRM_FORMAT_XBGR,
@@ -39,7 +39,7 @@ static const uint32_t formats_01[] = {
DRM_FORMAT_NV24,
 };
 
-static const uint32_t formats_234[] = {
+static const uint32_t formats_win_lite[] = {
DRM_FORMAT_XRGB,
DRM_FORMAT_ARGB,
DRM_FORMAT_XBGR,
@@ -50,102 +50,103 @@ static const uint32_t formats_234[] = {
DRM_FORMAT_BGR565,
 };
 
-static const struct vop_scl_extension win_full_ext = {
-   .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
-   .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
-   .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
-   .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
-   .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
-   .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
-   .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
-   .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
-   .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
-   .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
-   .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
-   .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
-   .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
-   .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
-   .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
-   .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
-   .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
-   .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
-   .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
-   .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
-   .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
-};
-
-static const struct vop_scl_regs win_full_scl = {
-   .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0x, 0x0),
-   .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0x, 16),
-   .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0x, 0x0),
-   .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0x, 16),
-};
-
-static const struct vop_win_phy win01_data = {
-   .scl = _full_scl,
-   .data_formats = formats_01,
-   .nformats = ARRAY_SIZE(formats_01),
-   .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
-   .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
-   .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
-   .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
-   .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
-   .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
-   .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0x, 0),
-   .uv_mst = VOP_REG(WIN0_CBR_MST, 0x, 0),
-   .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
-   .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
-   .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
-   .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
-};
-
-static const struct vop_win_phy win23_data = {
-   .data_formats = formats_234,
-   .nformats = ARRAY_SIZE(formats_234),
-   .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
-   .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
-   .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
-   .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
-   .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
-   .yrgb_mst = VOP_REG(WIN2_MST0, 0x, 0),
-   .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
-   .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
-   .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
-};
-
-static const struct vop_ctrl ctrl_data = {
-   .standby = VOP_REG(SYS_CTRL, 0x1, 22),
-   .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
-   .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
-   .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
-   .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
-   .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
-   .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
-   .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
-   .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
-   .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
-   .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
-   .pin_pol =