Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
* Tero Kristo [190917 07:22]:
> On 24/07/2019 09:47, Tony Lindgren wrote:
> > * Suman Anna [190723 21:02]:
> > > Hi Tony,
> > >
> > > On 7/23/19 6:28 AM, Tony Lindgren wrote:
> > > > The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
> > > > Otherwise we get the following warning on beagle-x15:
> > ...
> > > > @@ -2962,9 +2958,8 @@
> > > > ;
> > > > /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> > > > clocks = <_clkctrl
> > > > DRA7_L4PER2_MCASP7_CLKCTRL 0>,
> > > > -<_clkctrl
> > > > DRA7_L4PER2_MCASP7_CLKCTRL 24>,
> > > > -<_clkctrl
> > > > DRA7_L4PER2_MCASP7_CLKCTRL 28>;
> > > > - clock-names = "fck", "ahclkx", "ahclkr";
> > > > +<_clkctrl
> > > > DRA7_L4PER2_MCASP7_CLKCTRL 24>;
> > > > + clock-names = "fck", "ahclkx";
> > >
> > > The equivalent change to MCASP8 is missing.
> >
> > Thanks for spotting it, probably should be set up the same way as
> > MCASP4 too looking at the TRM.
> >
> > Tero, care to check the dra7 mcasp clocks we have defined?
>
> Sorry, missed this earlier.
>
> >
> > $ grep MCASP drivers/clk/ti/clk-7xx.c
> > { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP,
> > "ipu-clkctrl::22" },
> > { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:0154:22" },
> > { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:015c:22" },
> > { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:016c:22" },
> > { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:0184:24" },
> > { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:018c:22" },
> > { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:01f8:22" },
> > { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP,
> > "l4per2-clkctrl:01fc:22" },
> >
> > Is bit 24 above correct for MCASP8 or should it too be 22 like
> > adjacent MCASP4 in the TRM?
>
> So yeah, mcasp8 is wrong here, should be 22 as rest of them. I did fix
> mcasp8 clocks partially when doing the conversion but missed the parenting
> here; it was completely broken before.
OK thanks, I'll post a patch to fix that and an updated mcasp dts fix.
Regards,
Tony
Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
On 24/07/2019 09:47, Tony Lindgren wrote:
* Suman Anna [190723 21:02]:
Hi Tony,
On 7/23/19 6:28 AM, Tony Lindgren wrote:
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
Otherwise we get the following warning on beagle-x15:
...
@@ -2962,9 +2958,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
The equivalent change to MCASP8 is missing.
Thanks for spotting it, probably should be set up the same way as
MCASP4 too looking at the TRM.
Tero, care to check the dra7 mcasp clocks we have defined?
Sorry, missed this earlier.
$ grep MCASP drivers/clk/ti/clk-7xx.c
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP,
"ipu-clkctrl::22" },
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:0184:24" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:01f8:22" },
{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:01fc:22" },
Is bit 24 above correct for MCASP8 or should it too be 22 like
adjacent MCASP4 in the TRM?
So yeah, mcasp8 is wrong here, should be 22 as rest of them. I did fix
mcasp8 clocks partially when doing the conversion but missed the
parenting here; it was completely broken before.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
* Suman Anna [190723 21:02]:
> Hi Tony,
>
> On 7/23/19 6:28 AM, Tony Lindgren wrote:
> > The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
> > Otherwise we get the following warning on beagle-x15:
...
> > @@ -2962,9 +2958,8 @@
> > ;
> > /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> > clocks = <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
> > -<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> > 24>,
> > -<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> > 28>;
> > - clock-names = "fck", "ahclkx", "ahclkr";
> > +<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> > 24>;
> > + clock-names = "fck", "ahclkx";
>
> The equivalent change to MCASP8 is missing.
Thanks for spotting it, probably should be set up the same way as
MCASP4 too looking at the TRM.
Tero, care to check the dra7 mcasp clocks we have defined?
$ grep MCASP drivers/clk/ti/clk-7xx.c
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP,
"ipu-clkctrl::22" },
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:0184:24" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:01f8:22" },
{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP,
"l4per2-clkctrl:01fc:22" },
Is bit 24 above correct for MCASP8 or should it too be 22 like
adjacent MCASP4 in the TRM?
Regards,
Tony
Re: [PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
Hi Tony,
On 7/23/19 6:28 AM, Tony Lindgren wrote:
> The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
> Otherwise we get the following warning on beagle-x15:
>
> ti-sysc 48468000.target-module: could not add child clock ahclkr: -19
>
> Fixes: 5241ccbf2819 ("ARM: dts: Add missing ranges for dra7 mcasp l3 ports")
> Signed-off-by: Tony Lindgren
> ---
> arch/arm/boot/dts/dra7-l4.dtsi | 25 ++---
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
> --- a/arch/arm/boot/dts/dra7-l4.dtsi
> +++ b/arch/arm/boot/dts/dra7-l4.dtsi
> @@ -2818,9 +2818,8 @@
> ;
> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> clocks = <_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
> - <_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
> 24>,
> - <_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
> 28>;
> - clock-names = "fck", "ahclkx", "ahclkr";
> + <_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
> 24>;
> + clock-names = "fck", "ahclkx";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x68000 0x2000>,
> @@ -2854,9 +2853,8 @@
> ;
> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> clocks = <_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
> - <_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
> 24>,
> - <_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
> 28>;
> - clock-names = "fck", "ahclkx", "ahclkr";
> + <_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
> 24>;
> + clock-names = "fck", "ahclkx";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x6c000 0x2000>,
> @@ -2890,9 +2888,8 @@
> ;
> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> clocks = <_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
> - <_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
> 24>,
> - <_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
> 28>;
> - clock-names = "fck", "ahclkx", "ahclkr";
> + <_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
> 24>;
> + clock-names = "fck", "ahclkx";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x7 0x2000>,
> @@ -2926,9 +2923,8 @@
> ;
> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> clocks = <_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
> - <_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
> 24>,
> - <_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
> 28>;
> - clock-names = "fck", "ahclkx", "ahclkr";
> + <_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
> 24>;
> + clock-names = "fck", "ahclkx";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x74000 0x2000>,
> @@ -2962,9 +2958,8 @@
> ;
> /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
> clocks = <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
> - <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> 24>,
> - <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> 28>;
> - clock-names = "fck", "ahclkx", "ahclkr";
> + <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
> 24>;
> + clock-names = "fck", "ahclkx";
The equivalent change to MCASP8 is missing.
regards
Suman
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x78000 0x2000>,
>
[PATCH 5/8] ARM: dts: Drop bogus ahclkr clocks for dra7 mcasp 3 to 8
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
Otherwise we get the following warning on beagle-x15:
ti-sysc 48468000.target-module: could not add child clock ahclkr: -19
Fixes: 5241ccbf2819 ("ARM: dts: Add missing ranges for dra7 mcasp l3 ports")
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dra7-l4.dtsi | 25 ++---
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -2818,9 +2818,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x68000 0x2000>,
@@ -2854,9 +2853,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x6c000 0x2000>,
@@ -2890,9 +2888,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7 0x2000>,
@@ -2926,9 +2923,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x74000 0x2000>,
@@ -2962,9 +2958,8 @@
;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
-<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
24>,
-<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
28>;
- clock-names = "fck", "ahclkx", "ahclkr";
+<_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL
24>;
+ clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x78000 0x2000>,
--
2.21.0
