[PATCH 6/7] dmaengine: ste_dma40: don't allow high priority dest event lines
From: Rabin Vincent
Hardware bug: when a logical channel is triggerred by a high priority
destination event line, an extra packet transaction is generated in case
of important data write response latency on previous logical channel A
and if the source transfer of current logical channel B is already
completed and if no other channel with a higher priority than B is
waiting for execution.
Software workaround: do not set the high priority level for the
destination event lines that trigger logical channels.
Signed-off-by: Rabin Vincent
Reviewed-by: Shreshtha Kumar Sahu
Acked-by: Linus Walleij
Signed-off-by: Fabio Baltieri
---
drivers/dma/ste_dma40.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index d8d58d9..f871df6 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2181,11 +2181,24 @@ static void __d40_set_prio_rt(struct d40_chan *d40c,
int dev_type, bool src)
{
bool realtime = d40c->dma_cfg.realtime;
bool highprio = d40c->dma_cfg.high_priority;
- u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
u32 event = D40_TYPE_TO_EVENT(dev_type);
u32 group = D40_TYPE_TO_GROUP(dev_type);
u32 bit = 1 << event;
+ u32 prioreg;
+
+ /*
+* Due to a hardware bug, in some cases a logical channel triggered by
+* a high priority destination event line can generate extra packet
+* transactions.
+*
+* The workaround is to not set the high priority level for the
+* destination event lines that trigger logical channels.
+*/
+ if (!src && chan_is_logical(d40c))
+ highprio = false;
+
+ prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
/* Destination event lines are stored in the upper halfword */
if (!src)
--
1.7.12.1
--
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[PATCH 6/7] dmaengine: ste_dma40: don't allow high priority dest event lines
From: Rabin Vincent rabin.vinc...@stericsson.com
Hardware bug: when a logical channel is triggerred by a high priority
destination event line, an extra packet transaction is generated in case
of important data write response latency on previous logical channel A
and if the source transfer of current logical channel B is already
completed and if no other channel with a higher priority than B is
waiting for execution.
Software workaround: do not set the high priority level for the
destination event lines that trigger logical channels.
Signed-off-by: Rabin Vincent rabin.vinc...@stericsson.com
Reviewed-by: Shreshtha Kumar Sahu shreshthakumar.s...@stericsson.com
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Fabio Baltieri fabio.balti...@linaro.org
---
drivers/dma/ste_dma40.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index d8d58d9..f871df6 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2181,11 +2181,24 @@ static void __d40_set_prio_rt(struct d40_chan *d40c,
int dev_type, bool src)
{
bool realtime = d40c-dma_cfg.realtime;
bool highprio = d40c-dma_cfg.high_priority;
- u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
u32 event = D40_TYPE_TO_EVENT(dev_type);
u32 group = D40_TYPE_TO_GROUP(dev_type);
u32 bit = 1 event;
+ u32 prioreg;
+
+ /*
+* Due to a hardware bug, in some cases a logical channel triggered by
+* a high priority destination event line can generate extra packet
+* transactions.
+*
+* The workaround is to not set the high priority level for the
+* destination event lines that trigger logical channels.
+*/
+ if (!src chan_is_logical(d40c))
+ highprio = false;
+
+ prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
/* Destination event lines are stored in the upper halfword */
if (!src)
--
1.7.12.1
--
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