[PATCH RESEND v3 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains the peripheral
interrupt router, which handles the routing of the interrupts
for the two CPU cores. Almost all peripheral interrupts are
handled by the router, hence we make the MSCM module as default
interrupt parent for the SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will used with, the
correct parent interrupt controller has to be assigned to the
MSCM node (GIC or NVIC). The driver takes care of the parent
interrupt controller specific needs (interrupt-cells).
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/vf500.dtsi | 128 ++-
arch/arm/boot/dts/vfxxx.dtsi | 42 ++
2 files changed, 46 insertions(+), 124 deletions(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index de67005..f18 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
soc {
- interrupt-parent = <>;
-
aips-bus@4000 {
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
@@ -40,132 +39,13 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = ;
+ interrupt-parent = <>;
clocks = < VF610_CLK_PLATFORM_BUS>;
};
};
};
};
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ,
- ;
- interrupt-names = "edma-tx", "edma-err";
-};
-
- {
- interrupts = ,
- ;
- interrupt-names = "edma-tx", "edma-err";
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
-};
-
- {
- interrupts = ;
+ {
+ interrupt-parent = <>;
};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 505969a..ccdb268 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -47,6 +47,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
+ interrupt-parent = <>;
ranges;
aips0: aips-bus@4000 {
@@ -55,6 +56,13 @@
#size-cells = <1>;
ranges;
+ mscm: mscm@40001000 {
+ compatible = "fsl,vf610-mscm", "syscon";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x40001000 0x1000>;
+ };
+
edma0: dma-controller@40018000 {
#dma-cells = <2>;
compatible = "fsl,vf610-edma";
@@ -62,6 +70,9 @@
<0x40024000 0x1000>,
<0x40025000 0x1000>;
dma-channels = <32>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names =
[PATCH RESEND v3 3/3] ARM: dts: vf610: add Miscellaneous System Control Module (MSCM)
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains the peripheral
interrupt router, which handles the routing of the interrupts
for the two CPU cores. Almost all peripheral interrupts are
handled by the router, hence we make the MSCM module as default
interrupt parent for the SoC.
In a earlier commit the interrupt nodes were moved out of the
peripheral nodes and specified in the CPU specific vf500.dtsi
device tree. This allowed to use the base device tree vfxxx.dtsi
also for a Cortex-M4 specific device tree, which uses different
interrupt nodes due to the NVIC interrupt controller. However,
since the interrupt parent for peripherals is the MSCM module
independently which CPU the device tree is used for, we can move
the interrupt nodes into the base device tree vfxxx.dtsi again.
Depending on which CPU this base device tree will used with, the
correct parent interrupt controller has to be assigned to the
MSCM node (GIC or NVIC). The driver takes care of the parent
interrupt controller specific needs (interrupt-cells).
Signed-off-by: Stefan Agner ste...@agner.ch
---
arch/arm/boot/dts/vf500.dtsi | 128 ++-
arch/arm/boot/dts/vfxxx.dtsi | 42 ++
2 files changed, 46 insertions(+), 124 deletions(-)
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index de67005..f18 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
};
soc {
- interrupt-parent = intc;
-
aips-bus@4000 {
intc: interrupt-controller@40002000 {
compatible = arm,cortex-a9-gic;
#interrupt-cells = 3;
interrupt-controller;
+ interrupt-parent = intc;
reg = 0x40003000 0x1000,
0x40002100 0x100;
};
@@ -40,132 +39,13 @@
compatible = arm,cortex-a9-global-timer;
reg = 0x40002200 0x20;
interrupts = GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-parent = intc;
clocks = clks VF610_CLK_PLATFORM_BUS;
};
};
};
};
-adc0 {
- interrupts = GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH;
-};
-
-adc1 {
- interrupts = GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH;
-};
-
-can0 {
- interrupts = GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH;
-};
-
-can1 {
- interrupts = GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH;
-};
-
-dspi0 {
- interrupts = GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH;
-};
-
-edma0 {
- interrupts = GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH,
- GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH;
- interrupt-names = edma-tx, edma-err;
-};
-
-edma1 {
- interrupts = GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH,
- GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH;
- interrupt-names = edma-tx, edma-err;
-};
-
-esdhc1 {
- interrupts = GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH;
-};
-
-fec0 {
- interrupts = GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH;
-};
-
-fec1 {
- interrupts = GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH;
-};
-
-ftm {
- interrupts = GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio1 {
- interrupts = GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio2 {
- interrupts = GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio3 {
- interrupts = GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio4 {
- interrupts = GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH;
-};
-
-gpio5 {
- interrupts = GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH;
-};
-
-i2c0 {
- interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
-};
-
-pit {
- interrupts = GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH;
-};
-
-qspi0 {
- interrupts = GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH;
-};
-
-sai2 {
- interrupts = GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart0 {
- interrupts = GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart1 {
- interrupts = GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart2 {
- interrupts = GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart3 {
- interrupts = GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart4 {
- interrupts = GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH;
-};
-
-uart5 {
- interrupts = GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbdev0 {
- interrupts = GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbh1 {
- interrupts = GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbphy0 {
- interrupts = GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH;
-};
-
-usbphy1 {
- interrupts = GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH;
+mscm {
+ interrupt-parent = intc;
};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 505969a..ccdb268 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -47,6 +47,7 @@
#address-cells = 1;
