Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Hi Georgi,
On 15.09.2020 23:40, Georgi Djakov wrote:
> On 9/9/20 17:47, Sylwester Nawrocki wrote:
>> On 09.09.2020 11:07, Georgi Djakov wrote:
>>> On 8/28/20 17:49, Sylwester Nawrocki wrote:
On 30.07.2020 14:28, Sylwester Nawrocki wrote:
> On 09.07.2020 23:04, Rob Herring wrote:
>> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
>>> Add documentation for new optional properties in the exynos bus nodes:
>>> samsung,interconnect-parent, #interconnect-cells, bus-width.
>>> These properties allow to specify the SoC interconnect structure which
>>> then allows the interconnect consumer devices to request specific
>>> bandwidth requirements.
>>> Signed-off-by: Artur Świgoń
>>> Signed-off-by: Sylwester Nawrocki
>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
Actually we could do without any new property if we used existing
interconnect
consumers binding to specify linking between the provider nodes. I think
those
exynos-bus nodes could well be considered both the interconnect providers
and consumers. The example would then be something along the lines
(yes, I know the bus node naming needs to be fixed):
soc {
bus_dmc: bus_dmc {
compatible = "samsung,exynos-bus";
/* ... */
samsung,data-clock-ratio = <4>;
#interconnect-cells = <0>;
};
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_leftbus _dmc>;
#interconnect-cells = <0>;
};
bus_display: bus_display {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_display _leftbus>;
>>>
>>> Hmm, bus_display being a consumer of itself is a bit odd? Did you mean:
>>> interconnects = <_dmc _leftbus>;
>>
>> Might be, but we would need to swap the phandles so
>> order is maintained, i.e. interconnects = <_leftbus _dmc>;
>
> Ok, i see. Thanks for clarifying! Currently the "interconnects" property is
> defined as a pair of initiator and target nodes. You can keep it also as
> interconnects = <_display _dmc>, but you will need to figure out
> during probe that there is another node in the middle and defer. I assume
> that if a provider is also an interconnect consumer, we will link it to
> whatever nodes are specified in the "interconnects" property?
My apologies for the delay.
Yes, the "interconnect" property would be used (only) to determine what
links should be created.
>> My intention here was to describe the 'bus_display -> bus_leftbus' part
>> of data path 'bus_display -> bus_leftbus -> bus_dmc', bus_display is
>> really a consumer of 'bus_leftbus -> bus_dmc' path.
>>
>> I'm not sure if it is allowed to specify only single phandle (and
>> interconnect provider specifier) in the interconnect property, that would
>> be needed for the bus_leftbus node to define bus_dmc as the interconnect
>> destination port. There seems to be such a use case in arch/arm64/boot/
>> dts/allwinner/sun50i-a64.dtsi.
>
> In the general case you have to specify pairs. The "dma-mem" is a reserved
> name for devices that perform DMA through another bus with separate address
> translation rules.
I see, thanks for clarifying.
>>> I can't understand the above example with bus_display being it's own
>>> consumer.
>>> This seems strange to me. Could you please clarify it?
>>
>>> Otherwise the interconnect consumer DT bindings are already well established
>>> and i don't see anything preventing a node to be both consumer and provider.
>>> So this should be okay in general.
>>
>> Thanks, below is an updated example according to your suggestions.
>> Does it look better now?
>>
>> ---8<--
>> soc {
>> bus_dmc: bus_dmc {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> samsung,data-clock-ratio = <4>;
>> #interconnect-cells = <0>;
>> };
>>
>> bus_leftbus: bus_leftbus {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> interconnects = <_dmc>;
>> #interconnect-cells = <0>;
>> };
>>
>> bus_display: bus_display {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> interconnects = <_leftbus _dmc>;
>> #interconnect-cells = <0>;
>> };
>>
>> {
>> compatible = "samsung,exynos4212-mixer";
>> interconnects = <_display _dmc>;
>> /* ... */
>> };
>> };
>> ---8<--
>
> It's difficult to have a common way to describe
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Hi Sylwester,
On 9/9/20 17:47, Sylwester Nawrocki wrote:
> Hi Georgi,
>
> On 09.09.2020 11:07, Georgi Djakov wrote:
>> On 8/28/20 17:49, Sylwester Nawrocki wrote:
>>> On 30.07.2020 14:28, Sylwester Nawrocki wrote:
On 09.07.2020 23:04, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
>> Add documentation for new optional properties in the exynos bus nodes:
>> samsung,interconnect-parent, #interconnect-cells, bus-width.
>> These properties allow to specify the SoC interconnect structure which
>> then allows the interconnect consumer devices to request specific
>> bandwidth requirements.
>>
>> Signed-off-by: Artur Świgoń
>> Signed-off-by: Sylwester Nawrocki
>>>
>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>
>> +Optional properties for interconnect functionality (QoS frequency
>> constraints):
>> +- samsung,interconnect-parent: phandle to the parent interconnect node;
>> for
>> + passive devices should point to same node as the exynos,parent-bus
>> property.
>>>
> Adding vendor specific properties for a common binding defeats the
> point.
>>>
>>> Actually we could do without any new property if we used existing
>>> interconnect
>>> consumers binding to specify linking between the provider nodes. I think
>>> those
>>> exynos-bus nodes could well be considered both the interconnect providers
>>> and consumers. The example would then be something along the lines
>>> (yes, I know the bus node naming needs to be fixed):
>>>
>>> soc {
>>> bus_dmc: bus_dmc {
>>> compatible = "samsung,exynos-bus";
>>> /* ... */
>>> samsung,data-clock-ratio = <4>;
>>> #interconnect-cells = <0>;
>>> };
>>>
>>> bus_leftbus: bus_leftbus {
>>> compatible = "samsung,exynos-bus";
>>> /* ... */
>>> interconnects = <_leftbus _dmc>;
>>> #interconnect-cells = <0>;
>>> };
>>>
>>> bus_display: bus_display {
>>> compatible = "samsung,exynos-bus";
>>> /* ... */
>>> interconnects = <_display _leftbus>;
>>
>> Hmm, bus_display being a consumer of itself is a bit odd? Did you mean:
>> interconnects = <_dmc _leftbus>;
>
> Might be, but we would need to swap the phandles so
> order is maintained, i.e. interconnects = <_leftbus _dmc>;
Ok, i see. Thanks for clarifying! Currently the "interconnects" property is
defined as a pair of initiator and target nodes. You can keep it also as
interconnects = <_display _dmc>, but you will need to figure out
during probe that there is another node in the middle and defer. I assume
that if a provider is also an interconnect consumer, we will link it to
whatever nodes are specified in the "interconnects" property?
> My intention here was to describe the 'bus_display -> bus_leftbus' part
> of data path 'bus_display -> bus_leftbus -> bus_dmc', bus_display is
> really a consumer of 'bus_leftbus -> bus_dmc' path.
>
> I'm not sure if it is allowed to specify only single phandle (and
> interconnect provider specifier) in the interconnect property, that would
> be needed for the bus_leftbus node to define bus_dmc as the interconnect
> destination port. There seems to be such a use case in arch/arm64/boot/
> dts/allwinner/sun50i-a64.dtsi.
In the general case you have to specify pairs. The "dma-mem" is a reserved
name for devices that perform DMA through another bus with separate address
translation rules.
>>> #interconnect-cells = <0>;
>>> };
>>>
>>>
>>> {
>>> compatible = "samsung,exynos4212-mixer";
>>> interconnects = <_display _dmc>;
>>> /* ... */
>>> };
>>> };
>>>
>>> What do you think, Georgi, Rob?
>>
>> I can't understand the above example with bus_display being it's own
>> consumer.
>> This seems strange to me. Could you please clarify it?
>
>> Otherwise the interconnect consumer DT bindings are already well established
>> and i don't see anything preventing a node to be both consumer and provider.
>> So this should be okay in general.
>
> Thanks, below is an updated example according to your suggestions.
> Does it look better now?
>
> ---8<--
> soc {
> bus_dmc: bus_dmc {
> compatible = "samsung,exynos-bus";
> /* ... */
> samsung,data-clock-ratio = <4>;
> #interconnect-cells = <0>;
> };
>
> bus_leftbus: bus_leftbus {
> compatible = "samsung,exynos-bus";
> /* ... */
> interconnects = <_dmc>;
>
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Hi Georgi,
On 09.09.2020 11:07, Georgi Djakov wrote:
> On 8/28/20 17:49, Sylwester Nawrocki wrote:
>> On 30.07.2020 14:28, Sylwester Nawrocki wrote:
>>> On 09.07.2020 23:04, Rob Herring wrote:
On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
> Add documentation for new optional properties in the exynos bus nodes:
> samsung,interconnect-parent, #interconnect-cells, bus-width.
> These properties allow to specify the SoC interconnect structure which
> then allows the interconnect consumer devices to request specific
> bandwidth requirements.
>
> Signed-off-by: Artur Świgoń
> Signed-off-by: Sylwester Nawrocki
>>
> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> +Optional properties for interconnect functionality (QoS frequency
> constraints):
> +- samsung,interconnect-parent: phandle to the parent interconnect node;
> for
> + passive devices should point to same node as the exynos,parent-bus
> property.
>>
Adding vendor specific properties for a common binding defeats the
point.
>>
>> Actually we could do without any new property if we used existing
>> interconnect
>> consumers binding to specify linking between the provider nodes. I think
>> those
>> exynos-bus nodes could well be considered both the interconnect providers
>> and consumers. The example would then be something along the lines
>> (yes, I know the bus node naming needs to be fixed):
>>
>> soc {
>> bus_dmc: bus_dmc {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> samsung,data-clock-ratio = <4>;
>> #interconnect-cells = <0>;
>> };
>>
>> bus_leftbus: bus_leftbus {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> interconnects = <_leftbus _dmc>;
>> #interconnect-cells = <0>;
>> };
>>
>> bus_display: bus_display {
>> compatible = "samsung,exynos-bus";
>> /* ... */
>> interconnects = <_display _leftbus>;
>
> Hmm, bus_display being a consumer of itself is a bit odd? Did you mean:
> interconnects = <_dmc _leftbus>;
Might be, but we would need to swap the phandles so
order is maintained, i.e. interconnects = <_leftbus _dmc>;
My intention here was to describe the 'bus_display -> bus_leftbus' part
of data path 'bus_display -> bus_leftbus -> bus_dmc', bus_display is
really a consumer of 'bus_leftbus -> bus_dmc' path.
I'm not sure if it is allowed to specify only single phandle (and
interconnect provider specifier) in the interconnect property, that would
be needed for the bus_leftbus node to define bus_dmc as the interconnect
destination port. There seems to be such a use case in arch/arm64/boot/
dts/allwinner/sun50i-a64.dtsi.
>> #interconnect-cells = <0>;
>> };
>>
>>
>> {
>> compatible = "samsung,exynos4212-mixer";
>> interconnects = <_display _dmc>;
>> /* ... */
>> };
>> };
>>
>> What do you think, Georgi, Rob?
>
> I can't understand the above example with bus_display being it's own consumer.
> This seems strange to me. Could you please clarify it?
> Otherwise the interconnect consumer DT bindings are already well established
> and i don't see anything preventing a node to be both consumer and provider.
> So this should be okay in general.
Thanks, below is an updated example according to your suggestions.
Does it look better now?
---8<--
soc {
bus_dmc: bus_dmc {
compatible = "samsung,exynos-bus";
/* ... */
samsung,data-clock-ratio = <4>;
#interconnect-cells = <0>;
};
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_dmc>;
#interconnect-cells = <0>;
};
bus_display: bus_display {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_leftbus _dmc>;
#interconnect-cells = <0>;
};
{
compatible = "samsung,exynos4212-mixer";
interconnects = <_display _dmc>;
/* ... */
};
};
---8<--
--
Regards,
Sylwester
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Hi Sylwester,
On 8/28/20 17:49, Sylwester Nawrocki wrote:
> On 30.07.2020 14:28, Sylwester Nawrocki wrote:
>> On 09.07.2020 23:04, Rob Herring wrote:
>>> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
Add documentation for new optional properties in the exynos bus nodes:
samsung,interconnect-parent, #interconnect-cells, bus-width.
These properties allow to specify the SoC interconnect structure which
then allows the interconnect consumer devices to request specific
bandwidth requirements.
Signed-off-by: Artur Świgoń
Signed-off-by: Sylwester Nawrocki
>
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -51,6 +51,13 @@ Optional properties only for parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate
the performance count against total cycle count.
+Optional properties for interconnect functionality (QoS frequency
constraints):
+- samsung,interconnect-parent: phandle to the parent interconnect node;
for
+ passive devices should point to same node as the exynos,parent-bus
property.
>
>>> Adding vendor specific properties for a common binding defeats the
>>> point.
>
> Actually we could do without any new property if we used existing interconnect
> consumers binding to specify linking between the provider nodes. I think those
> exynos-bus nodes could well be considered both the interconnect providers
> and consumers. The example would then be something along the lines
> (yes, I know the bus node naming needs to be fixed):
>
> soc {
> bus_dmc: bus_dmc {
> compatible = "samsung,exynos-bus";
> /* ... */
> samsung,data-clock-ratio = <4>;
> #interconnect-cells = <0>;
> };
>
> bus_leftbus: bus_leftbus {
> compatible = "samsung,exynos-bus";
> /* ... */
> interconnects = <_leftbus _dmc>;
> #interconnect-cells = <0>;
> };
>
> bus_display: bus_display {
> compatible = "samsung,exynos-bus";
> /* ... */
> interconnects = <_display _leftbus>;
Hmm, bus_display being a consumer of itself is a bit odd? Did you mean:
interconnects = <_dmc _leftbus>;
> #interconnect-cells = <0>;
> };
>
>
>{
> compatible = "samsung,exynos4212-mixer";
> interconnects = <_display _dmc>;
> /* ... */
> };
> };
>
> What do you think, Georgi, Rob?
I can't understand the above example with bus_display being it's own consumer.
This seems strange to me. Could you please clarify it?
Otherwise the interconnect consumer DT bindings are already well established
and i don't see anything preventing a node to be both consumer and provider.
So this should be okay in general.
Thanks,
Georgi
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
On 30.07.2020 14:28, Sylwester Nawrocki wrote:
> On 09.07.2020 23:04, Rob Herring wrote:
>> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
>>> Add documentation for new optional properties in the exynos bus nodes:
>>> samsung,interconnect-parent, #interconnect-cells, bus-width.
>>> These properties allow to specify the SoC interconnect structure which
>>> then allows the interconnect consumer devices to request specific
>>> bandwidth requirements.
>>>
>>> Signed-off-by: Artur Świgoń
>>> Signed-off-by: Sylwester Nawrocki
>>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>>> @@ -51,6 +51,13 @@ Optional properties only for parent bus device:
>>> - exynos,saturation-ratio: the percentage value which is used to calibrate
>>> the performance count against total cycle count.
>>>
>>> +Optional properties for interconnect functionality (QoS frequency
>>> constraints):
>>> +- samsung,interconnect-parent: phandle to the parent interconnect node; for
>>> + passive devices should point to same node as the exynos,parent-bus
>>> property.
>> Adding vendor specific properties for a common binding defeats the
>> point.
Actually we could do without any new property if we used existing interconnect
consumers binding to specify linking between the provider nodes. I think those
exynos-bus nodes could well be considered both the interconnect providers
and consumers. The example would then be something along the lines
(yes, I know the bus node naming needs to be fixed):
soc {
bus_dmc: bus_dmc {
compatible = "samsung,exynos-bus";
/* ... */
samsung,data-clock-ratio = <4>;
#interconnect-cells = <0>;
};
bus_leftbus: bus_leftbus {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_leftbus _dmc>;
#interconnect-cells = <0>;
};
bus_display: bus_display {
compatible = "samsung,exynos-bus";
/* ... */
interconnects = <_display _leftbus>;
#interconnect-cells = <0>;
};
{
compatible = "samsung,exynos4212-mixer";
interconnects = <_display _dmc>;
/* ... */
};
};
What do you think, Georgi, Rob?
--
Regards
Sylwester
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
On 09.07.2020 23:04, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
>> Add documentation for new optional properties in the exynos bus nodes:
>> samsung,interconnect-parent, #interconnect-cells, bus-width.
>> These properties allow to specify the SoC interconnect structure which
>> then allows the interconnect consumer devices to request specific
>> bandwidth requirements.
>>
>> Signed-off-by: Artur Świgoń
>> Signed-off-by: Sylwester Nawrocki
>> ---
>> .../devicetree/bindings/devfreq/exynos-bus.txt | 68
>> +-
>> 1 file changed, 66 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> index e71f752..4035e3e 100644
>> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
>> @@ -51,6 +51,13 @@ Optional properties only for parent bus device:
>> - exynos,saturation-ratio: the percentage value which is used to calibrate
>> the performance count against total cycle count.
>>
>> +Optional properties for interconnect functionality (QoS frequency
>> constraints):
>> +- samsung,interconnect-parent: phandle to the parent interconnect node; for
>> + passive devices should point to same node as the exynos,parent-bus
>> property.
>
> Adding vendor specific properties for a common binding defeats the
> point.
Should we make it then a common interconnect-parent property? Perhaps allowing
also a second cell after the phandle to indicate the target interconnect id?
Currently the links are only being defined in drivers, I'm not sure if we want
to go that direction and extend the interconnect binding so it is possible
to define any link between the nodes.
With the samsung,interconnect-parent property there was an assumption that
each DT node ("samsung,exynos-bus" compatible) corresponds to an interconnect
provider with single interconnect node. The source and destination node id
for the link were unspecified and dynamically allocated by the driver.
I guess we don't want a property that would contain pairs of the interconnect
node specifiers (phandle + interconnect id) to define all links, since usually
additional data is required per each link.
Then perhaps we could make the new interconnect-parent property applicable
only to DT nodes with #interconnect-cells == 0, i.e. valid only in such DT
nodes?
>> +- #interconnect-cells: should be 0.
>> +- bus-width: the interconnect bus width in bits, default value is 8 when
>> this
>> + property is missing.
>
> Your bus is 8-bits or 4-bits as the example?
Bus width might not be a good term for the intended purpose of that property.
It has been added to specify minimum bus clock rate required for given data
throughput. After checking the documentation again the AXI bus width is
actually 128 bits everywhere for instance. The example defines data path
leftbus <- dmc <- (memory) and for leftbus we have bus-width=<8> and for dmc
bus-width=<4>.
Perhaps it's better to use a vendor specific property instead, e.g.
samsung, data-clock-ratio?
--
Thanks,
Sylwester
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
On Thu, Jul 02, 2020 at 06:37:19PM +0200, Sylwester Nawrocki wrote:
> Add documentation for new optional properties in the exynos bus nodes:
> samsung,interconnect-parent, #interconnect-cells, bus-width.
> These properties allow to specify the SoC interconnect structure which
> then allows the interconnect consumer devices to request specific
> bandwidth requirements.
>
> Signed-off-by: Artur Świgoń
> Signed-off-by: Sylwester Nawrocki
> ---
> Changes for v6:
> - added dts example of bus hierarchy definition and the interconnect
>consumer,
> - added new bus-width property.
>
> Changes for v5:
> - exynos,interconnect-parent-node renamed to samsung,interconnect-parent
> ---
> .../devicetree/bindings/devfreq/exynos-bus.txt | 68
> +-
> 1 file changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> index e71f752..4035e3e 100644
> --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -51,6 +51,13 @@ Optional properties only for parent bus device:
> - exynos,saturation-ratio: the percentage value which is used to calibrate
> the performance count against total cycle count.
>
> +Optional properties for interconnect functionality (QoS frequency
> constraints):
> +- samsung,interconnect-parent: phandle to the parent interconnect node; for
> + passive devices should point to same node as the exynos,parent-bus
> property.
Adding vendor specific properties for a common binding defeats the
point.
> +- #interconnect-cells: should be 0.
> +- bus-width: the interconnect bus width in bits, default value is 8 when this
> + property is missing.
Your bus is 8-bits or 4-bits as the example?
> +
> Detailed correlation between sub-blocks and power line according to Exynos
> SoC:
> - In case of Exynos3250, there are two power line as following:
> VDD_MIF |--- DMC
> @@ -135,7 +142,7 @@ Detailed correlation between sub-blocks and power line
> according to Exynos SoC:
> |--- PERIC (Fixed clock rate)
> |--- FSYS (Fixed clock rate)
>
> -Example1:
> +Example 1:
> Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
> power line (regulator). The MIF (Memory Interface) AXI bus is used to
> transfer data between DRAM and CPU and uses the VDD_MIF regulator.
> @@ -184,7 +191,7 @@ Example1:
> |L5 |20 |20 |40 |30 | ||100 |
> --
>
> -Example2 :
> +Example 2:
> The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
> is listed below:
>
> @@ -419,3 +426,60 @@ Example2 :
> devfreq = <_leftbus>;
> status = "okay";
> };
> +
> +Example 3:
> + An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
> + Exynos4412 SoC with video mixer as an interconnect consumer device.
> +
> + soc {
> + bus_dmc: bus_dmc {
> + compatible = "samsung,exynos-bus";
> + clocks = < CLK_DIV_DMC>;
> + clock-names = "bus";
> + operating-points-v2 = <_dmc_opp_table>;
> + bus-width = <4>;
> + #interconnect-cells = <0>;
> + status = "disabled";
> + };
> +
> + bus_leftbus: bus_leftbus {
> + compatible = "samsung,exynos-bus";
> + clocks = < CLK_DIV_GDL>;
> + clock-names = "bus";
> + operating-points-v2 = <_leftbus_opp_table>;
> + samsung,interconnect-parent = <_dmc>;
> + #interconnect-cells = <0>;
> + status = "disabled";
> + };
> +
> + bus_display: bus_display {
> + compatible = "samsung,exynos-bus";
> + clocks = < CLK_ACLK160>;
> + clock-names = "bus";
> + operating-points-v2 = <_display_opp_table>;
> + samsung,interconnect-parent = <_leftbus>;
> + #interconnect-cells = <0>;
> + status = "disabled";
> + };
> +
> + bus_dmc_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + /* ... */
> + }
> +
> + bus_leftbus_opp_table: opp_table3 {
> + compatible = "operating-points-v2";
> + /* ... */
> + };
> +
> + bus_display_opp_table: opp_table4 {
> + compatible = "operating-points-v2";
> + /* .. */
> + };
> +
> + {
> + compatible =
Re: [PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Hi Sylwester, On 7/3/20 1:37 AM, Sylwester Nawrocki wrote: > Add documentation for new optional properties in the exynos bus nodes: > samsung,interconnect-parent, #interconnect-cells, bus-width. > These properties allow to specify the SoC interconnect structure which > then allows the interconnect consumer devices to request specific > bandwidth requirements. > > Signed-off-by: Artur Świgoń > Signed-off-by: Sylwester Nawrocki > --- > Changes for v6: > - added dts example of bus hierarchy definition and the interconnect >consumer, > - added new bus-width property. > > Changes for v5: > - exynos,interconnect-parent-node renamed to samsung,interconnect-parent > --- > .../devicetree/bindings/devfreq/exynos-bus.txt | 68 > +- > 1 file changed, 66 insertions(+), 2 deletions(-) Acked-by: Chanwoo Choi (snip) -- Best Regards, Chanwoo Choi Samsung Electronics
[PATCH RFC v6 1/6] dt-bindings: exynos-bus: Add documentation for interconnect properties
Add documentation for new optional properties in the exynos bus nodes:
samsung,interconnect-parent, #interconnect-cells, bus-width.
These properties allow to specify the SoC interconnect structure which
then allows the interconnect consumer devices to request specific
bandwidth requirements.
Signed-off-by: Artur Świgoń
Signed-off-by: Sylwester Nawrocki
---
Changes for v6:
- added dts example of bus hierarchy definition and the interconnect
consumer,
- added new bus-width property.
Changes for v5:
- exynos,interconnect-parent-node renamed to samsung,interconnect-parent
---
.../devicetree/bindings/devfreq/exynos-bus.txt | 68 +-
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index e71f752..4035e3e 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -51,6 +51,13 @@ Optional properties only for parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate
the performance count against total cycle count.
+Optional properties for interconnect functionality (QoS frequency constraints):
+- samsung,interconnect-parent: phandle to the parent interconnect node; for
+ passive devices should point to same node as the exynos,parent-bus property.
+- #interconnect-cells: should be 0.
+- bus-width: the interconnect bus width in bits, default value is 8 when this
+ property is missing.
+
Detailed correlation between sub-blocks and power line according to Exynos SoC:
- In case of Exynos3250, there are two power line as following:
VDD_MIF |--- DMC
@@ -135,7 +142,7 @@ Detailed correlation between sub-blocks and power line
according to Exynos SoC:
|--- PERIC (Fixed clock rate)
|--- FSYS (Fixed clock rate)
-Example1:
+Example 1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to
transfer data between DRAM and CPU and uses the VDD_MIF regulator.
@@ -184,7 +191,7 @@ Example1:
|L5 |20 |20 |40 |30 | ||100 |
--
-Example2 :
+Example 2:
The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
is listed below:
@@ -419,3 +426,60 @@ Example2 :
devfreq = <_leftbus>;
status = "okay";
};
+
+Example 3:
+ An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
+ Exynos4412 SoC with video mixer as an interconnect consumer device.
+
+ soc {
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <_dmc_opp_table>;
+ bus-width = <4>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <_leftbus_opp_table>;
+ samsung,interconnect-parent = <_dmc>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = < CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <_display_opp_table>;
+ samsung,interconnect-parent = <_leftbus>;
+ #interconnect-cells = <0>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ /* ... */
+ }
+
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ /* ... */
+ };
+
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ /* .. */
+ };
+
+{
+ compatible = "samsung,exynos4212-mixer";
+ interconnects = <_display _dmc>;
+ /* ... */
+ };
+ };
--
2.7.4
