Re: [PATCH V2 01/19] csky: Build infrastructure
On Tue, Jul 03, 2018 at 06:03:04PM +0200, Arnd Bergmann wrote: > It looks like the CK8xx CPUs are basically compatible, so it would > be nice to have a way to configure a kernel that can run on all > of them, picking a safe default for options that depend on a > particular CPU. E.g. when only CK860 supports SMP, you might > start out by making SMP "depend on !(CPU_CK807 || CPU_CK810)", > as an alternative to implementing a way for an SMP-enabled kernel > to run on non-SMP CPUs (arm has that, but it's probably too complex > for your needs). > > Similarly, you can set L1_CACHE_BYTES to the largest possible > size, and make things like CPU_TLB_SIZE dynamically detected. We talked about this topic in the last patchsets. Ck807/810/860 are mutually incompatible in kernel level but both can run user space programs in ck807/810. On Wed, Mar 28, 2018 at 09:40:49AM +0200, Arnd Bergmann wrote: > Ok, thanks for the clarification. Obviously if they are mutually incompatible, > there is no point in using a common kernel, so your current version is > absolutely fine, and this is similar to how we cannot have a common kernel > between ARMv5, ARMv7-A and ARMv7-M, which are all incompatible > at the kernel level. Yes. > One more question for my understanding: Are the three types of ck8xx > CPUs mutually incompatible in user space as well, or are the differences > only for the kernel? For the ARM example, ARMv5 and ARMv7 > fundamentally require separate kernels, but both can run user space > programs built for ARMv5. -mcpu=ck807 app could run on ck807, ck810, ck860. -mcpu=ck810 app could run on ck807, ck810, ck860. -mcpu=ck860 app only run on ck860. They are all incompatible at the kernel level. > > +menu "C-SKY Debug Options" > > +config CSKY_DEBUG_INFO > > + bool "Compile the kernel with debug info, just add -g" > > + depends on !DEBUG_INFO > > + help > > + DEBUG_INFO and COMPILE_TEST is conflict, so we provide > > + another way to support -g. > > + Some drivers eg: DW_MMC need COMPILE_TEST for new cpu > > + arch :( > > Just send a patch to change those dependencies, there is no reason > not to apply those. Generally speaking, the kernel should not contain > workarounds for particular (mis-)features of the kernel, when you can > just change those. Ok. > > +generic-y += atomic.h > > The asm-generic version of atomic.h is a bit inefficient, > you might want to provide an optimized version for your > architecture. Ok. > > +generic-y += auxvec.h > > You should not need asm/auxvec.h or uapi/asm/auxvec.h Ok. > > +generic-y += bug.h > > providing your own bug.h might be helpful too. > Have a look Ok. > > +generic-y += cputime.h > > asm-generic/cputime.h no loinger exists Ok, remove it. > > +generic-y += kvm_para.h > > Do you support KVM? No, remove it, thx. > > +generic-y += sizes.h > > Deprecated and should not be needed Ok, remove it. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Tue, Jul 03, 2018 at 06:03:04PM +0200, Arnd Bergmann wrote: > It looks like the CK8xx CPUs are basically compatible, so it would > be nice to have a way to configure a kernel that can run on all > of them, picking a safe default for options that depend on a > particular CPU. E.g. when only CK860 supports SMP, you might > start out by making SMP "depend on !(CPU_CK807 || CPU_CK810)", > as an alternative to implementing a way for an SMP-enabled kernel > to run on non-SMP CPUs (arm has that, but it's probably too complex > for your needs). > > Similarly, you can set L1_CACHE_BYTES to the largest possible > size, and make things like CPU_TLB_SIZE dynamically detected. We talked about this topic in the last patchsets. Ck807/810/860 are mutually incompatible in kernel level but both can run user space programs in ck807/810. On Wed, Mar 28, 2018 at 09:40:49AM +0200, Arnd Bergmann wrote: > Ok, thanks for the clarification. Obviously if they are mutually incompatible, > there is no point in using a common kernel, so your current version is > absolutely fine, and this is similar to how we cannot have a common kernel > between ARMv5, ARMv7-A and ARMv7-M, which are all incompatible > at the kernel level. Yes. > One more question for my understanding: Are the three types of ck8xx > CPUs mutually incompatible in user space as well, or are the differences > only for the kernel? For the ARM example, ARMv5 and ARMv7 > fundamentally require separate kernels, but both can run user space > programs built for ARMv5. -mcpu=ck807 app could run on ck807, ck810, ck860. -mcpu=ck810 app could run on ck807, ck810, ck860. -mcpu=ck860 app only run on ck860. They are all incompatible at the kernel level. > > +menu "C-SKY Debug Options" > > +config CSKY_DEBUG_INFO > > + bool "Compile the kernel with debug info, just add -g" > > + depends on !DEBUG_INFO > > + help > > + DEBUG_INFO and COMPILE_TEST is conflict, so we provide > > + another way to support -g. > > + Some drivers eg: DW_MMC need COMPILE_TEST for new cpu > > + arch :( > > Just send a patch to change those dependencies, there is no reason > not to apply those. Generally speaking, the kernel should not contain > workarounds for particular (mis-)features of the kernel, when you can > just change those. Ok. > > +generic-y += atomic.h > > The asm-generic version of atomic.h is a bit inefficient, > you might want to provide an optimized version for your > architecture. Ok. > > +generic-y += auxvec.h > > You should not need asm/auxvec.h or uapi/asm/auxvec.h Ok. > > +generic-y += bug.h > > providing your own bug.h might be helpful too. > Have a look Ok. > > +generic-y += cputime.h > > asm-generic/cputime.h no loinger exists Ok, remove it. > > +generic-y += kvm_para.h > > Do you support KVM? No, remove it, thx. > > +generic-y += sizes.h > > Deprecated and should not be needed Ok, remove it. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Sun, Jul 1, 2018 at 7:30 PM, Guo Ren wrote: > Signed-off-by: Guo Ren > +choice > + prompt "CPU MODEL" > + default CPU_CK610 > + > +config CPU_CK610 > + bool "CSKY CPU ck610" > + select CPU_NEED_TLBSYNC > + select CPU_NEED_SOFTALIGN > + select CPU_NO_USER_BKPT > + > +config CPU_CK810 > + bool "CSKY CPU ck810" > + select CPU_HAS_HILO > + select CPU_NEED_TLBSYNC > + > +config CPU_CK807 > + bool "CSKY CPU ck807" > + select CPU_HAS_HILO > + > +config CPU_CK860 > + bool "CSKY CPU ck860" > + select CPU_HAS_TLBI > + select CPU_HAS_CACHEV2 > + select CPU_HAS_LDSTEX > +endchoice It looks like the CK8xx CPUs are basically compatible, so it would be nice to have a way to configure a kernel that can run on all of them, picking a safe default for options that depend on a particular CPU. E.g. when only CK860 supports SMP, you might start out by making SMP "depend on !(CPU_CK807 || CPU_CK810)", as an alternative to implementing a way for an SMP-enabled kernel to run on non-SMP CPUs (arm has that, but it's probably too complex for your needs). Similarly, you can set L1_CACHE_BYTES to the largest possible size, and make things like CPU_TLB_SIZE dynamically detected. > +menu "C-SKY Debug Options" > +config CSKY_DEBUG_INFO > + bool "Compile the kernel with debug info, just add -g" > + depends on !DEBUG_INFO > + help > + DEBUG_INFO and COMPILE_TEST is conflict, so we provide > + another way to support -g. > + Some drivers eg: DW_MMC need COMPILE_TEST for new cpu > + arch :( Just send a patch to change those dependencies, there is no reason not to apply those. Generally speaking, the kernel should not contain workarounds for particular (mis-)features of the kernel, when you can just change those. > diff --git a/arch/csky/include/asm/Kbuild b/arch/csky/include/asm/Kbuild > new file mode 100644 > index 000..5de6519 > --- /dev/null > +++ b/arch/csky/include/asm/Kbuild > @@ -0,0 +1,72 @@ > +generic-y += asm-offsets.h > +generic-y += atomic.h The asm-generic version of atomic.h is a bit inefficient, you might want to provide an optimized version for your architecture. > +generic-y += auxvec.h You should not need asm/auxvec.h or uapi/asm/auxvec.h > +generic-y += bitsperlong.h > +generic-y += bug.h providing your own bug.h might be helpful too. Have a look > +generic-y += bugs.h > +generic-y += clkdev.h > +generic-y += cputime.h asm-generic/cputime.h no loinger exists > +generic-y += kvm_para.h Do you support KVM? > +generic-y += sizes.h Deprecated and should not be needed Arnd
Re: [PATCH V2 01/19] csky: Build infrastructure
On Sun, Jul 1, 2018 at 7:30 PM, Guo Ren wrote: > Signed-off-by: Guo Ren > +choice > + prompt "CPU MODEL" > + default CPU_CK610 > + > +config CPU_CK610 > + bool "CSKY CPU ck610" > + select CPU_NEED_TLBSYNC > + select CPU_NEED_SOFTALIGN > + select CPU_NO_USER_BKPT > + > +config CPU_CK810 > + bool "CSKY CPU ck810" > + select CPU_HAS_HILO > + select CPU_NEED_TLBSYNC > + > +config CPU_CK807 > + bool "CSKY CPU ck807" > + select CPU_HAS_HILO > + > +config CPU_CK860 > + bool "CSKY CPU ck860" > + select CPU_HAS_TLBI > + select CPU_HAS_CACHEV2 > + select CPU_HAS_LDSTEX > +endchoice It looks like the CK8xx CPUs are basically compatible, so it would be nice to have a way to configure a kernel that can run on all of them, picking a safe default for options that depend on a particular CPU. E.g. when only CK860 supports SMP, you might start out by making SMP "depend on !(CPU_CK807 || CPU_CK810)", as an alternative to implementing a way for an SMP-enabled kernel to run on non-SMP CPUs (arm has that, but it's probably too complex for your needs). Similarly, you can set L1_CACHE_BYTES to the largest possible size, and make things like CPU_TLB_SIZE dynamically detected. > +menu "C-SKY Debug Options" > +config CSKY_DEBUG_INFO > + bool "Compile the kernel with debug info, just add -g" > + depends on !DEBUG_INFO > + help > + DEBUG_INFO and COMPILE_TEST is conflict, so we provide > + another way to support -g. > + Some drivers eg: DW_MMC need COMPILE_TEST for new cpu > + arch :( Just send a patch to change those dependencies, there is no reason not to apply those. Generally speaking, the kernel should not contain workarounds for particular (mis-)features of the kernel, when you can just change those. > diff --git a/arch/csky/include/asm/Kbuild b/arch/csky/include/asm/Kbuild > new file mode 100644 > index 000..5de6519 > --- /dev/null > +++ b/arch/csky/include/asm/Kbuild > @@ -0,0 +1,72 @@ > +generic-y += asm-offsets.h > +generic-y += atomic.h The asm-generic version of atomic.h is a bit inefficient, you might want to provide an optimized version for your architecture. > +generic-y += auxvec.h You should not need asm/auxvec.h or uapi/asm/auxvec.h > +generic-y += bitsperlong.h > +generic-y += bug.h providing your own bug.h might be helpful too. Have a look > +generic-y += bugs.h > +generic-y += clkdev.h > +generic-y += cputime.h asm-generic/cputime.h no loinger exists > +generic-y += kvm_para.h Do you support KVM? > +generic-y += sizes.h Deprecated and should not be needed Arnd
Re: [PATCH V2 01/19] csky: Build infrastructure
On Mon, Jul 02, 2018 at 09:33:51PM -0600, Rob Herring wrote: > > +config CSKY_BUILTIN_DTB > > + bool "Use kernel builtin dtb" > > + > > +config CSKY_BUILTIN_DTB_NAME > > + string "kernel builtin dtb name" > > + depends on CSKY_BUILTIN_DTB > > +endmenu > > These options generally exist for backwards compatibility with legacy > bootloaders that don't support DT which shouldn't apply here given > this is a new arch. If we need this for other reasons, it should not > be an architecture specific option. We want the BUILTIN_DTB for some boards and they don't need change dtb at all. And I just follow other archs BUILTIN_DTB in their Kconfig. eg: xtensa, h8300, mips, nds32, sh, openrisc, arc ... I just keep this in Kconfig.debug and it's not a recommended method. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Mon, Jul 02, 2018 at 09:33:51PM -0600, Rob Herring wrote: > > +config CSKY_BUILTIN_DTB > > + bool "Use kernel builtin dtb" > > + > > +config CSKY_BUILTIN_DTB_NAME > > + string "kernel builtin dtb name" > > + depends on CSKY_BUILTIN_DTB > > +endmenu > > These options generally exist for backwards compatibility with legacy > bootloaders that don't support DT which shouldn't apply here given > this is a new arch. If we need this for other reasons, it should not > be an architecture specific option. We want the BUILTIN_DTB for some boards and they don't need change dtb at all. And I just follow other archs BUILTIN_DTB in their Kconfig. eg: xtensa, h8300, mips, nds32, sh, openrisc, arc ... I just keep this in Kconfig.debug and it's not a recommended method. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On Sun, Jul 1, 2018 at 11:36 AM Guo Ren wrote: > > Signed-off-by: Guo Ren > --- [...] > +config CSKY_BUILTIN_DTB > + bool "Use kernel builtin dtb" > + > +config CSKY_BUILTIN_DTB_NAME > + string "kernel builtin dtb name" > + depends on CSKY_BUILTIN_DTB > +endmenu These options generally exist for backwards compatibility with legacy bootloaders that don't support DT which shouldn't apply here given this is a new arch. If we need this for other reasons, it should not be an architecture specific option. Rob
Re: [PATCH V2 01/19] csky: Build infrastructure
On Sun, Jul 1, 2018 at 11:36 AM Guo Ren wrote: > > Signed-off-by: Guo Ren > --- [...] > +config CSKY_BUILTIN_DTB > + bool "Use kernel builtin dtb" > + > +config CSKY_BUILTIN_DTB_NAME > + string "kernel builtin dtb name" > + depends on CSKY_BUILTIN_DTB > +endmenu These options generally exist for backwards compatibility with legacy bootloaders that don't support DT which shouldn't apply here given this is a new arch. If we need this for other reasons, it should not be an architecture specific option. Rob
Re: [PATCH V2 01/19] csky: Build infrastructure
Hi Randy, On Sun, Jul 01, 2018 at 02:01:52PM -0700, Randy Dunlap wrote: > Hi, > Just a few comments... > Thx for your review. I'll fixup all of you mentioned and self-check again. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
Hi Randy, On Sun, Jul 01, 2018 at 02:01:52PM -0700, Randy Dunlap wrote: > Hi, > Just a few comments... > Thx for your review. I'll fixup all of you mentioned and self-check again. Guo Ren
Re: [PATCH V2 01/19] csky: Build infrastructure
On 07/01/18 10:30, Guo Ren wrote: > Signed-off-by: Guo Ren > --- Hi, Just a few comments... > > diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig > new file mode 100644 > index 000..cfeb312 > --- /dev/null > +++ b/arch/csky/Kconfig > @@ -0,0 +1,211 @@ > +config CSKY > + bool > + default y shorter: def_bool y > + select ARCH_USE_BUILTIN_BSWAP > + select COMMON_CLK > + select CLKSRC_MMIO > + select CLKSRC_OF > + select IRQ_DOMAIN > + select HANDLE_DOMAIN_IRQ > + select DW_APB_TIMER_OF > + select GENERIC_ATOMIC64 > + select GENERIC_CLOCKEVENTS > + select GENERIC_CPU_DEVICES > + select GENERIC_IRQ_CHIP > + select GENERIC_IRQ_PROBE > + select GENERIC_IRQ_SHOW > + select GENERIC_SCHED_CLOCK > + select GENERIC_SMP_IDLE_THREAD > + select HAVE_ARCH_TRACEHOOK > + select HAVE_GENERIC_DMA_COHERENT > + select HAVE_KERNEL_GZIP > + select HAVE_KERNEL_LZO > + select HAVE_KERNEL_LZMA > + select HAVE_PERF_EVENTS > + select HAVE_C_RECORDMCOUNT > + select HAVE_KPROBES > + select HAVE_KRETPROBES > + select HAVE_DMA_API_DEBUG > + select HAVE_MEMBLOCK > + select MAY_HAVE_SPARSE_IRQ > + select MODULES_USE_ELF_RELA if MODULES > + select NO_BOOTMEM > + select OF > + select OF_EARLY_FLATTREE > + select OF_RESERVED_MEM > + select PERF_USE_VMALLOC > + select RTC_LIB > + select TIMER_OF > + select USB_ARCH_HAS_EHCI > + select USB_ARCH_HAS_OHCI > + > +config CPU_HAS_CACHEV2 > + bool > + > +config CPU_HAS_HILO > + bool > + > +config CPU_HAS_TLBI > + bool > + > +config CPU_HAS_LDSTEX > + bool > + help > + For SMP cpu need "ldex" instrcutions to keep atomic. For SMP, CPU needs instructions for atomic operations. > + > +config CPU_NEED_TLBSYNC > + bool > + > +config CPU_NEED_SOFTALIGN > + bool > + > +config CPU_NO_USER_BKPT > + bool > + help > + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, > because > + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. > + So we need a 16bit instruction as user space bkpt, and it will cause > a illegal cause an illegal > + instruction exception. > + In kernel we parse the *regs->pc to determine wether send SIGTRAP or > not. whether to send > + > +config GENERIC_CALIBRATE_DELAY > + bool > + default y def_bool y > + > +config HZ > + int > + default 100 > + > +config GENERIC_CSUM > + bool > + default y def_bool y > + > +config GENERIC_HWEIGHT > + bool > + default y def_bool y > + > +config MMU > + bool > + default y same. > + > +config RWSEM_GENERIC_SPINLOCK > + bool > + default y same. > + > +config TIME_LOW_RES > + bool > + default y again. > + > +config TRACE_IRQFLAGS_SUPPORT > + bool > + default y again. > + > +source "init/Kconfig" > + > +source "kernel/Kconfig.freezer" > + > +menu "Processor type and features" > + > +comment "Processor type" > + > +choice > + prompt "CPU MODEL" > + default CPU_CK610 > + > +config CPU_CK610 > + bool "CSKY CPU ck610" > + select CPU_NEED_TLBSYNC > + select CPU_NEED_SOFTALIGN > + select CPU_NO_USER_BKPT > + > +config CPU_CK810 > + bool "CSKY CPU ck810" > + select CPU_HAS_HILO > + select CPU_NEED_TLBSYNC > + > +config CPU_CK807 > + bool "CSKY CPU ck807" > + select CPU_HAS_HILO > + > +config CPU_CK860 > + bool "CSKY CPU ck860" > + select CPU_HAS_TLBI > + select CPU_HAS_CACHEV2 > + select CPU_HAS_LDSTEX > +endchoice > + > +config CPU_TLB_SIZE > + int > + default "128" if(CPU_CK610 || CPU_CK807 || CPU_CK810) > + default "1024" if(CPU_CK860) > + > +config CPU_ASID_BITS > + int > + default "8" if(CPU_CK610 || CPU_CK807 || CPU_CK810) > + default "12"if(CPU_CK860) > + > +config L1_CACHE_SHIFT > + int > + default "4" if(CPU_CK610) > + default "5" if(CPU_CK807 || CPU_CK810) > + default "6" if(CPU_CK860) prefer a space after "if" on all those lines above. > + > +config HIGHMEM > + bool "High Memory Support" > + depends on !CPU_CK610 > + default y > + > +menuconfig CPU_HAS_FPU > + bool "CPU has FPU coprocessor" > + depends on CPU_CK807 || CPU_CK810 || CPU_CK860 > + > +menuconfig CPU_HAS_TEE > + bool "CPU has Trusted Execution Environment" > + depends on CPU_CK810 > + > +config SMP > + bool "Symmetric Multi-Processing (SMP) support for C-SKY" > + depends on CPU_CK860 > + default n > + > +config NR_CPUS > + int "Maximum number of CPUs (2-32)" > + range 2 32 > + depends on SMP > + default "4" > + > +comment "*System type*" > + > +config RAM_BASE > + hex "It must be the
Re: [PATCH V2 01/19] csky: Build infrastructure
On 07/01/18 10:30, Guo Ren wrote: > Signed-off-by: Guo Ren > --- Hi, Just a few comments... > > diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig > new file mode 100644 > index 000..cfeb312 > --- /dev/null > +++ b/arch/csky/Kconfig > @@ -0,0 +1,211 @@ > +config CSKY > + bool > + default y shorter: def_bool y > + select ARCH_USE_BUILTIN_BSWAP > + select COMMON_CLK > + select CLKSRC_MMIO > + select CLKSRC_OF > + select IRQ_DOMAIN > + select HANDLE_DOMAIN_IRQ > + select DW_APB_TIMER_OF > + select GENERIC_ATOMIC64 > + select GENERIC_CLOCKEVENTS > + select GENERIC_CPU_DEVICES > + select GENERIC_IRQ_CHIP > + select GENERIC_IRQ_PROBE > + select GENERIC_IRQ_SHOW > + select GENERIC_SCHED_CLOCK > + select GENERIC_SMP_IDLE_THREAD > + select HAVE_ARCH_TRACEHOOK > + select HAVE_GENERIC_DMA_COHERENT > + select HAVE_KERNEL_GZIP > + select HAVE_KERNEL_LZO > + select HAVE_KERNEL_LZMA > + select HAVE_PERF_EVENTS > + select HAVE_C_RECORDMCOUNT > + select HAVE_KPROBES > + select HAVE_KRETPROBES > + select HAVE_DMA_API_DEBUG > + select HAVE_MEMBLOCK > + select MAY_HAVE_SPARSE_IRQ > + select MODULES_USE_ELF_RELA if MODULES > + select NO_BOOTMEM > + select OF > + select OF_EARLY_FLATTREE > + select OF_RESERVED_MEM > + select PERF_USE_VMALLOC > + select RTC_LIB > + select TIMER_OF > + select USB_ARCH_HAS_EHCI > + select USB_ARCH_HAS_OHCI > + > +config CPU_HAS_CACHEV2 > + bool > + > +config CPU_HAS_HILO > + bool > + > +config CPU_HAS_TLBI > + bool > + > +config CPU_HAS_LDSTEX > + bool > + help > + For SMP cpu need "ldex" instrcutions to keep atomic. For SMP, CPU needs instructions for atomic operations. > + > +config CPU_NEED_TLBSYNC > + bool > + > +config CPU_NEED_SOFTALIGN > + bool > + > +config CPU_NO_USER_BKPT > + bool > + help > + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, > because > + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. > + So we need a 16bit instruction as user space bkpt, and it will cause > a illegal cause an illegal > + instruction exception. > + In kernel we parse the *regs->pc to determine wether send SIGTRAP or > not. whether to send > + > +config GENERIC_CALIBRATE_DELAY > + bool > + default y def_bool y > + > +config HZ > + int > + default 100 > + > +config GENERIC_CSUM > + bool > + default y def_bool y > + > +config GENERIC_HWEIGHT > + bool > + default y def_bool y > + > +config MMU > + bool > + default y same. > + > +config RWSEM_GENERIC_SPINLOCK > + bool > + default y same. > + > +config TIME_LOW_RES > + bool > + default y again. > + > +config TRACE_IRQFLAGS_SUPPORT > + bool > + default y again. > + > +source "init/Kconfig" > + > +source "kernel/Kconfig.freezer" > + > +menu "Processor type and features" > + > +comment "Processor type" > + > +choice > + prompt "CPU MODEL" > + default CPU_CK610 > + > +config CPU_CK610 > + bool "CSKY CPU ck610" > + select CPU_NEED_TLBSYNC > + select CPU_NEED_SOFTALIGN > + select CPU_NO_USER_BKPT > + > +config CPU_CK810 > + bool "CSKY CPU ck810" > + select CPU_HAS_HILO > + select CPU_NEED_TLBSYNC > + > +config CPU_CK807 > + bool "CSKY CPU ck807" > + select CPU_HAS_HILO > + > +config CPU_CK860 > + bool "CSKY CPU ck860" > + select CPU_HAS_TLBI > + select CPU_HAS_CACHEV2 > + select CPU_HAS_LDSTEX > +endchoice > + > +config CPU_TLB_SIZE > + int > + default "128" if(CPU_CK610 || CPU_CK807 || CPU_CK810) > + default "1024" if(CPU_CK860) > + > +config CPU_ASID_BITS > + int > + default "8" if(CPU_CK610 || CPU_CK807 || CPU_CK810) > + default "12"if(CPU_CK860) > + > +config L1_CACHE_SHIFT > + int > + default "4" if(CPU_CK610) > + default "5" if(CPU_CK807 || CPU_CK810) > + default "6" if(CPU_CK860) prefer a space after "if" on all those lines above. > + > +config HIGHMEM > + bool "High Memory Support" > + depends on !CPU_CK610 > + default y > + > +menuconfig CPU_HAS_FPU > + bool "CPU has FPU coprocessor" > + depends on CPU_CK807 || CPU_CK810 || CPU_CK860 > + > +menuconfig CPU_HAS_TEE > + bool "CPU has Trusted Execution Environment" > + depends on CPU_CK810 > + > +config SMP > + bool "Symmetric Multi-Processing (SMP) support for C-SKY" > + depends on CPU_CK860 > + default n > + > +config NR_CPUS > + int "Maximum number of CPUs (2-32)" > + range 2 32 > + depends on SMP > + default "4" > + > +comment "*System type*" > + > +config RAM_BASE > + hex "It must be the
[PATCH V2 01/19] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 211 + arch/csky/Kconfig.debug| 29 + arch/csky/Makefile | 92 ++ arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 4 + arch/csky/boot/Makefile| 25 arch/csky/boot/dts/Makefile| 14 +++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 72 +++ arch/csky/include/uapi/asm/Kbuild | 33 ++ arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 511 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..cfeb312 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,211 @@ +config CSKY + bool + default y + select ARCH_USE_BUILTIN_BSWAP + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_PERF_EVENTS + select HAVE_C_RECORDMCOUNT + select HAVE_KPROBES + select HAVE_KRETPROBES + select HAVE_DMA_API_DEBUG + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP cpu need "ldex" instrcutions to keep atomic. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause a illegal + instruction exception. + In kernel we parse the *regs->pc to determine wether send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config HZ + int + default 100 + +config GENERIC_CSUM + bool + default y + +config GENERIC_HWEIGHT + bool + default y + +config MMU + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config TIME_LOW_RES + bool + default y + +config TRACE_IRQFLAGS_SUPPORT + bool + default y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +comment "Processor type" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY CPU ck610" + select CPU_NEED_TLBSYNC + select CPU_NEED_SOFTALIGN + select CPU_NO_USER_BKPT + +config CPU_CK810 + bool "CSKY CPU ck810" + select CPU_HAS_HILO + select CPU_NEED_TLBSYNC + +config CPU_CK807 + bool "CSKY CPU ck807" + select CPU_HAS_HILO + +config CPU_CK860 + bool "CSKY CPU ck860" + select CPU_HAS_TLBI + select CPU_HAS_CACHEV2 + select CPU_HAS_LDSTEX +endchoice + +config CPU_TLB_SIZE + int + default "128" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if(CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if(CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if(CPU_CK610) + default "5" if(CPU_CK807 || CPU_CK810) + default "6"
[PATCH V2 01/19] csky: Build infrastructure
Signed-off-by: Guo Ren --- arch/csky/Kconfig | 211 + arch/csky/Kconfig.debug| 29 + arch/csky/Makefile | 92 ++ arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 4 + arch/csky/boot/Makefile| 25 arch/csky/boot/dts/Makefile| 14 +++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 72 +++ arch/csky/include/uapi/asm/Kbuild | 33 ++ arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 ++ 13 files changed, 511 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..cfeb312 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,211 @@ +config CSKY + bool + default y + select ARCH_USE_BUILTIN_BSWAP + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_PERF_EVENTS + select HAVE_C_RECORDMCOUNT + select HAVE_KPROBES + select HAVE_KRETPROBES + select HAVE_DMA_API_DEBUG + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP cpu need "ldex" instrcutions to keep atomic. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause a illegal + instruction exception. + In kernel we parse the *regs->pc to determine wether send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config HZ + int + default 100 + +config GENERIC_CSUM + bool + default y + +config GENERIC_HWEIGHT + bool + default y + +config MMU + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config TIME_LOW_RES + bool + default y + +config TRACE_IRQFLAGS_SUPPORT + bool + default y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "Processor type and features" + +comment "Processor type" + +choice + prompt "CPU MODEL" + default CPU_CK610 + +config CPU_CK610 + bool "CSKY CPU ck610" + select CPU_NEED_TLBSYNC + select CPU_NEED_SOFTALIGN + select CPU_NO_USER_BKPT + +config CPU_CK810 + bool "CSKY CPU ck810" + select CPU_HAS_HILO + select CPU_NEED_TLBSYNC + +config CPU_CK807 + bool "CSKY CPU ck807" + select CPU_HAS_HILO + +config CPU_CK860 + bool "CSKY CPU ck860" + select CPU_HAS_TLBI + select CPU_HAS_CACHEV2 + select CPU_HAS_LDSTEX +endchoice + +config CPU_TLB_SIZE + int + default "128" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if(CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if(CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if(CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if(CPU_CK610) + default "5" if(CPU_CK807 || CPU_CK810) + default "6"
