Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-06-02 Thread Boris Brezillon 
On Sat, 28 May 2016 17:54:10 +0800
Keguang Zhang  wrote:

> From: Kelvin Cheung 
> 
> This patch adds NAND driver for Loongson1B.
> 
> Signed-off-by: Kelvin Cheung 
> 
> ---
> v3:
>Replace __raw_readl/__raw_writel with readl/writel.
>Split ls1x_nand into two structures: ls1x_nand_chip and 
> ls1x_nand_controller.
> V2:
>Modify the dependency in Kconfig due to the changes of DMA module.
> ---
>  drivers/mtd/nand/Kconfig  |   8 +
>  drivers/mtd/nand/Makefile |   1 +
>  drivers/mtd/nand/loongson1_nand.c | 555 
> ++
>  3 files changed, 564 insertions(+)
>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index f05e0e9..be20fb8 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
> Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> controller. This controller is found on IPQ806x SoC.
>  
> +config MTD_NAND_LOONGSON1
> + tristate "Support for Loongson1 SoC NAND controller"
> + depends on MACH_LOONGSON32
> + select DMADEVICES
> + select LOONGSON1_DMA
> + help
> + Enables support for NAND Flash on Loongson1 SoC based boards.
> +
>  endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index f553353..0310c0b 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)+= sunxi_nand.o
>  obj-$(CONFIG_MTD_NAND_HISI504)   += hisi504_nand.o
>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
> +obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1_nand.o
>  
>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/loongson1_nand.c 
> b/drivers/mtd/nand/loongson1_nand.c
> new file mode 100644
> index 000..86831773
> --- /dev/null
> +++ b/drivers/mtd/nand/loongson1_nand.c
> @@ -0,0 +1,555 @@
> +/*
> + * NAND Flash Driver for Loongson 1 SoC
> + *
> + * Copyright (C) 2015-2016 Zhang, Keguang 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/* Loongson 1 NAND Register Definitions */
> +#define NAND_CMD 0x0
> +#define NAND_ADDRL   0x4
> +#define NAND_ADDRH   0x8
> +#define NAND_TIMING  0xc
> +#define NAND_IDL 0x10
> +#define NAND_IDH 0x14
> +#define NAND_STATUS  0x14
> +#define NAND_PARAM   0x18
> +#define NAND_OP_NUM  0x1c
> +#define NAND_CS_RDY  0x20
> +
> +#define NAND_DMA_ADDR0x40
> +
> +/* NAND Command Register Bits */
> +#define OP_DONE  BIT(10)
> +#define OP_SPARE BIT(9)
> +#define OP_MAIN  BIT(8)
> +#define CMD_STATUS   BIT(7)
> +#define CMD_RESETBIT(6)
> +#define CMD_READID   BIT(5)
> +#define BLOCKS_ERASE BIT(4)
> +#define CMD_ERASEBIT(3)
> +#define CMD_WRITEBIT(2)
> +#define CMD_READ BIT(1)
> +#define CMD_VALIDBIT(0)
> +
> +#define  LS1X_NAND_TIMEOUT   20
> +
> +/* macros for registers read/write */
> +#define nand_readl(nandc, off)   \
> + readl((nandc)->reg_base + (off))
> +
> +#define nand_writel(nandc, off, val) \
> + writel((val), (nandc)->reg_base + (off))
> +
> +#define set_cmd(nandc, ctrl) \
> + nand_writel(nandc, NAND_CMD, ctrl)
> +
> +#define start_nand(nandc)\
> + nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
> +
> +struct ls1x_nand_chip {
> + struct nand_chip chip;
> + struct plat_ls1x_nand *pdata;
> +};
> +
> +struct ls1x_nand_controller {

ls1x_nand_controller should inherit from nand_hw_ctrl.

struct nand_hw_ctrl base;

> + struct clk *clk;
> + void __iomem *reg_base;
> +
> + int cmd_ctrl;
> + char datareg[8];
> + char *data_ptr;
> +
> + /* DMA stuff */
> + unsigned char *dma_buf;
> + unsigned int buf_off;
> + unsigned int buf_len;
> +
> + /* DMA Engine stuff */
> + unsigned int dma_chan_id;
> + struct dma_chan *dma_chan;
> + dma_cookie_t dma_cookie;
> + struct completion dma_complete;
> + void __iomem *dma_desc;
> +};
> +
> +static inline struct ls1x_nand_chip *to_ls1x_nand_chip(struct mtd_info *mtd)
> +{
> + return container_of(mtd_to_nand(mtd), struct ls1x_nand_chip, chip);
> +}
> +
> +static void dma_callback(void

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-06-02 Thread Boris Brezillon 
On Sat, 28 May 2016 17:54:10 +0800
Keguang Zhang  wrote:

> From: Kelvin Cheung 
> 
> This patch adds NAND driver for Loongson1B.
> 
> Signed-off-by: Kelvin Cheung 
> 
> ---
> v3:
>Replace __raw_readl/__raw_writel with readl/writel.
>Split ls1x_nand into two structures: ls1x_nand_chip and 
> ls1x_nand_controller.
> V2:
>Modify the dependency in Kconfig due to the changes of DMA module.
> ---
>  drivers/mtd/nand/Kconfig  |   8 +
>  drivers/mtd/nand/Makefile |   1 +
>  drivers/mtd/nand/loongson1_nand.c | 555 
> ++
>  3 files changed, 564 insertions(+)
>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index f05e0e9..be20fb8 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
> Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> controller. This controller is found on IPQ806x SoC.
>  
> +config MTD_NAND_LOONGSON1
> + tristate "Support for Loongson1 SoC NAND controller"
> + depends on MACH_LOONGSON32
> + select DMADEVICES
> + select LOONGSON1_DMA
> + help
> + Enables support for NAND Flash on Loongson1 SoC based boards.
> +
>  endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index f553353..0310c0b 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)+= sunxi_nand.o
>  obj-$(CONFIG_MTD_NAND_HISI504)   += hisi504_nand.o
>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
> +obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1_nand.o
>  
>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/loongson1_nand.c 
> b/drivers/mtd/nand/loongson1_nand.c
> new file mode 100644
> index 000..86831773
> --- /dev/null
> +++ b/drivers/mtd/nand/loongson1_nand.c
> @@ -0,0 +1,555 @@
> +/*
> + * NAND Flash Driver for Loongson 1 SoC
> + *
> + * Copyright (C) 2015-2016 Zhang, Keguang 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/* Loongson 1 NAND Register Definitions */
> +#define NAND_CMD 0x0
> +#define NAND_ADDRL   0x4
> +#define NAND_ADDRH   0x8
> +#define NAND_TIMING  0xc
> +#define NAND_IDL 0x10
> +#define NAND_IDH 0x14
> +#define NAND_STATUS  0x14
> +#define NAND_PARAM   0x18
> +#define NAND_OP_NUM  0x1c
> +#define NAND_CS_RDY  0x20
> +
> +#define NAND_DMA_ADDR0x40
> +
> +/* NAND Command Register Bits */
> +#define OP_DONE  BIT(10)
> +#define OP_SPARE BIT(9)
> +#define OP_MAIN  BIT(8)
> +#define CMD_STATUS   BIT(7)
> +#define CMD_RESETBIT(6)
> +#define CMD_READID   BIT(5)
> +#define BLOCKS_ERASE BIT(4)
> +#define CMD_ERASEBIT(3)
> +#define CMD_WRITEBIT(2)
> +#define CMD_READ BIT(1)
> +#define CMD_VALIDBIT(0)
> +
> +#define  LS1X_NAND_TIMEOUT   20
> +
> +/* macros for registers read/write */
> +#define nand_readl(nandc, off)   \
> + readl((nandc)->reg_base + (off))
> +
> +#define nand_writel(nandc, off, val) \
> + writel((val), (nandc)->reg_base + (off))
> +
> +#define set_cmd(nandc, ctrl) \
> + nand_writel(nandc, NAND_CMD, ctrl)
> +
> +#define start_nand(nandc)\
> + nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
> +
> +struct ls1x_nand_chip {
> + struct nand_chip chip;
> + struct plat_ls1x_nand *pdata;
> +};
> +
> +struct ls1x_nand_controller {

ls1x_nand_controller should inherit from nand_hw_ctrl.

struct nand_hw_ctrl base;

> + struct clk *clk;
> + void __iomem *reg_base;
> +
> + int cmd_ctrl;
> + char datareg[8];
> + char *data_ptr;
> +
> + /* DMA stuff */
> + unsigned char *dma_buf;
> + unsigned int buf_off;
> + unsigned int buf_len;
> +
> + /* DMA Engine stuff */
> + unsigned int dma_chan_id;
> + struct dma_chan *dma_chan;
> + dma_cookie_t dma_cookie;
> + struct completion dma_complete;
> + void __iomem *dma_desc;
> +};
> +
> +static inline struct ls1x_nand_chip *to_ls1x_nand_chip(struct mtd_info *mtd)
> +{
> + return container_of(mtd_to_nand(mtd), struct ls1x_nand_chip, chip);
> +}
> +
> +static void dma_callback(void *data)
> +{
> + struct mtd_info *mtd = (struct mtd_info *)data;
> + struct nand_chip *chip =

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Kelvin Cheung 
Hi Boris,
I have the same feeling as Mychaela, and suffered from the 'high-level
controllers' as well.
Looking forward to your review, thanks!

Best regards,

Keguang Zhang

On 05/28/2016 08:12 PM, Boris Brezillon wrote:
> Hi Kelvin,
>
> On Sat, 28 May 2016 17:54:10 +0800
> Keguang Zhang  wrote:
>
>> From: Kelvin Cheung 
>>
>> This patch adds NAND driver for Loongson1B.
> I think your controller matches Mychaela's "high-level NAND controller"
> definition [1]. Mychaela, can you confirm the Loongson controller
> looks like yours?
>
> I'll do a detailed review of the code soon.
>
> Thanks,
>
> Boris
>
> [1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346
>
>> Signed-off-by: Kelvin Cheung 
>>
>> ---
>> v3:
>>Replace __raw_readl/__raw_writel with readl/writel.
>>Split ls1x_nand into two structures: ls1x_nand_chip and 
>> ls1x_nand_controller.
>> V2:
>>Modify the dependency in Kconfig due to the changes of DMA module.
>> ---
>>  drivers/mtd/nand/Kconfig  |   8 +
>>  drivers/mtd/nand/Makefile |   1 +
>>  drivers/mtd/nand/loongson1_nand.c | 555 
>> ++
>>  3 files changed, 564 insertions(+)
>>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index f05e0e9..be20fb8 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
>>Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>>controller. This controller is found on IPQ806x SoC.
>>  
>> +config MTD_NAND_LOONGSON1
>> +tristate "Support for Loongson1 SoC NAND controller"
>> +depends on MACH_LOONGSON32
>> +select DMADEVICES
>> +select LOONGSON1_DMA
>> +help
>> +Enables support for NAND Flash on Loongson1 SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index f553353..0310c0b 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)   += sunxi_nand.o
>>  obj-$(CONFIG_MTD_NAND_HISI504)  += hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> +obj-$(CONFIG_MTD_NAND_LOONGSON1)+= loongson1_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/loongson1_nand.c 
>> b/drivers/mtd/nand/loongson1_nand.c
>> new file mode 100644
>> index 000..86831773
>> --- /dev/null
>> +++ b/drivers/mtd/nand/loongson1_nand.c
>> @@ -0,0 +1,555 @@
>> +/*
>> + * NAND Flash Driver for Loongson 1 SoC
>> + *
>> + * Copyright (C) 2015-2016 Zhang, Keguang 
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +/* Loongson 1 NAND Register Definitions */
>> +#define NAND_CMD0x0
>> +#define NAND_ADDRL  0x4
>> +#define NAND_ADDRH  0x8
>> +#define NAND_TIMING 0xc
>> +#define NAND_IDL0x10
>> +#define NAND_IDH0x14
>> +#define NAND_STATUS 0x14
>> +#define NAND_PARAM  0x18
>> +#define NAND_OP_NUM 0x1c
>> +#define NAND_CS_RDY 0x20
>> +
>> +#define NAND_DMA_ADDR   0x40
>> +
>> +/* NAND Command Register Bits */
>> +#define OP_DONE BIT(10)
>> +#define OP_SPAREBIT(9)
>> +#define OP_MAIN BIT(8)
>> +#define CMD_STATUS  BIT(7)
>> +#define CMD_RESET   BIT(6)
>> +#define CMD_READID  BIT(5)
>> +#define BLOCKS_ERASEBIT(4)
>> +#define CMD_ERASE   BIT(3)
>> +#define CMD_WRITE   BIT(2)
>> +#define CMD_READBIT(1)
>> +#define CMD_VALID   BIT(0)
>> +
>> +#define LS1X_NAND_TIMEOUT   20
>> +
>> +/* macros for registers read/write */
>> +#define nand_readl(nandc, off)  \
>> +readl((nandc)->reg_base + (off))
>> +
>> +#define nand_writel(nandc, off, val)\
>> +writel((val), (nandc)->reg_base + (off))
>> +
>> +#define set_cmd(nandc, ctrl)\
>> +nand_writel(nandc, NAND_CMD, ctrl)
>> +
>> +#define start_nand(nandc)   \
>> +nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
>> +
>> +struct ls1x_nand_chip {
>> +struct nand_chip chip;
>> +struct plat_ls1x_nand *pdata;
>> +};
>> +
>> +struct ls1x_nand_controller {
>> +struct clk *clk;
>> +void __iomem *reg_base;
>> +
>> +int cmd_ctrl;
>> +char datareg[8];
>> +char *data_ptr;
>> +

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Kelvin Cheung 
Hi Boris,
I have the same feeling as Mychaela, and suffered from the 'high-level
controllers' as well.
Looking forward to your review, thanks!

Best regards,

Keguang Zhang

On 05/28/2016 08:12 PM, Boris Brezillon wrote:
> Hi Kelvin,
>
> On Sat, 28 May 2016 17:54:10 +0800
> Keguang Zhang  wrote:
>
>> From: Kelvin Cheung 
>>
>> This patch adds NAND driver for Loongson1B.
> I think your controller matches Mychaela's "high-level NAND controller"
> definition [1]. Mychaela, can you confirm the Loongson controller
> looks like yours?
>
> I'll do a detailed review of the code soon.
>
> Thanks,
>
> Boris
>
> [1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346
>
>> Signed-off-by: Kelvin Cheung 
>>
>> ---
>> v3:
>>Replace __raw_readl/__raw_writel with readl/writel.
>>Split ls1x_nand into two structures: ls1x_nand_chip and 
>> ls1x_nand_controller.
>> V2:
>>Modify the dependency in Kconfig due to the changes of DMA module.
>> ---
>>  drivers/mtd/nand/Kconfig  |   8 +
>>  drivers/mtd/nand/Makefile |   1 +
>>  drivers/mtd/nand/loongson1_nand.c | 555 
>> ++
>>  3 files changed, 564 insertions(+)
>>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index f05e0e9..be20fb8 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
>>Enables support for NAND flash chips on SoCs containing the EBI2 NAND
>>controller. This controller is found on IPQ806x SoC.
>>  
>> +config MTD_NAND_LOONGSON1
>> +tristate "Support for Loongson1 SoC NAND controller"
>> +depends on MACH_LOONGSON32
>> +select DMADEVICES
>> +select LOONGSON1_DMA
>> +help
>> +Enables support for NAND Flash on Loongson1 SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index f553353..0310c0b 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)   += sunxi_nand.o
>>  obj-$(CONFIG_MTD_NAND_HISI504)  += hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> +obj-$(CONFIG_MTD_NAND_LOONGSON1)+= loongson1_nand.o
>>  
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
>> diff --git a/drivers/mtd/nand/loongson1_nand.c 
>> b/drivers/mtd/nand/loongson1_nand.c
>> new file mode 100644
>> index 000..86831773
>> --- /dev/null
>> +++ b/drivers/mtd/nand/loongson1_nand.c
>> @@ -0,0 +1,555 @@
>> +/*
>> + * NAND Flash Driver for Loongson 1 SoC
>> + *
>> + * Copyright (C) 2015-2016 Zhang, Keguang 
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include 
>> +
>> +/* Loongson 1 NAND Register Definitions */
>> +#define NAND_CMD0x0
>> +#define NAND_ADDRL  0x4
>> +#define NAND_ADDRH  0x8
>> +#define NAND_TIMING 0xc
>> +#define NAND_IDL0x10
>> +#define NAND_IDH0x14
>> +#define NAND_STATUS 0x14
>> +#define NAND_PARAM  0x18
>> +#define NAND_OP_NUM 0x1c
>> +#define NAND_CS_RDY 0x20
>> +
>> +#define NAND_DMA_ADDR   0x40
>> +
>> +/* NAND Command Register Bits */
>> +#define OP_DONE BIT(10)
>> +#define OP_SPAREBIT(9)
>> +#define OP_MAIN BIT(8)
>> +#define CMD_STATUS  BIT(7)
>> +#define CMD_RESET   BIT(6)
>> +#define CMD_READID  BIT(5)
>> +#define BLOCKS_ERASEBIT(4)
>> +#define CMD_ERASE   BIT(3)
>> +#define CMD_WRITE   BIT(2)
>> +#define CMD_READBIT(1)
>> +#define CMD_VALID   BIT(0)
>> +
>> +#define LS1X_NAND_TIMEOUT   20
>> +
>> +/* macros for registers read/write */
>> +#define nand_readl(nandc, off)  \
>> +readl((nandc)->reg_base + (off))
>> +
>> +#define nand_writel(nandc, off, val)\
>> +writel((val), (nandc)->reg_base + (off))
>> +
>> +#define set_cmd(nandc, ctrl)\
>> +nand_writel(nandc, NAND_CMD, ctrl)
>> +
>> +#define start_nand(nandc)   \
>> +nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
>> +
>> +struct ls1x_nand_chip {
>> +struct nand_chip chip;
>> +struct plat_ls1x_nand *pdata;
>> +};
>> +
>> +struct ls1x_nand_controller {
>> +struct clk *clk;
>> +void __iomem *reg_base;
>> +
>> +int cmd_ctrl;
>> +char datareg[8];
>> +char *data_ptr;
>> +
>> +/* DMA stuff */
>> +unsigned char *dma_buf;
>> +unsigned int buf_off;
>> +

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Boris Brezillon 
Hi Kelvin,

On Sat, 28 May 2016 17:54:10 +0800
Keguang Zhang  wrote:

> From: Kelvin Cheung 
> 
> This patch adds NAND driver for Loongson1B.

I think your controller matches Mychaela's "high-level NAND controller"
definition [1]. Mychaela, can you confirm the Loongson controller
looks like yours?

I'll do a detailed review of the code soon.

Thanks,

Boris

[1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346

> 
> Signed-off-by: Kelvin Cheung 
> 
> ---
> v3:
>Replace __raw_readl/__raw_writel with readl/writel.
>Split ls1x_nand into two structures: ls1x_nand_chip and 
> ls1x_nand_controller.
> V2:
>Modify the dependency in Kconfig due to the changes of DMA module.
> ---
>  drivers/mtd/nand/Kconfig  |   8 +
>  drivers/mtd/nand/Makefile |   1 +
>  drivers/mtd/nand/loongson1_nand.c | 555 
> ++
>  3 files changed, 564 insertions(+)
>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index f05e0e9..be20fb8 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
> Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> controller. This controller is found on IPQ806x SoC.
>  
> +config MTD_NAND_LOONGSON1
> + tristate "Support for Loongson1 SoC NAND controller"
> + depends on MACH_LOONGSON32
> + select DMADEVICES
> + select LOONGSON1_DMA
> + help
> + Enables support for NAND Flash on Loongson1 SoC based boards.
> +
>  endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index f553353..0310c0b 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)+= sunxi_nand.o
>  obj-$(CONFIG_MTD_NAND_HISI504)   += hisi504_nand.o
>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
> +obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1_nand.o
>  
>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/loongson1_nand.c 
> b/drivers/mtd/nand/loongson1_nand.c
> new file mode 100644
> index 000..86831773
> --- /dev/null
> +++ b/drivers/mtd/nand/loongson1_nand.c
> @@ -0,0 +1,555 @@
> +/*
> + * NAND Flash Driver for Loongson 1 SoC
> + *
> + * Copyright (C) 2015-2016 Zhang, Keguang 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/* Loongson 1 NAND Register Definitions */
> +#define NAND_CMD 0x0
> +#define NAND_ADDRL   0x4
> +#define NAND_ADDRH   0x8
> +#define NAND_TIMING  0xc
> +#define NAND_IDL 0x10
> +#define NAND_IDH 0x14
> +#define NAND_STATUS  0x14
> +#define NAND_PARAM   0x18
> +#define NAND_OP_NUM  0x1c
> +#define NAND_CS_RDY  0x20
> +
> +#define NAND_DMA_ADDR0x40
> +
> +/* NAND Command Register Bits */
> +#define OP_DONE  BIT(10)
> +#define OP_SPARE BIT(9)
> +#define OP_MAIN  BIT(8)
> +#define CMD_STATUS   BIT(7)
> +#define CMD_RESETBIT(6)
> +#define CMD_READID   BIT(5)
> +#define BLOCKS_ERASE BIT(4)
> +#define CMD_ERASEBIT(3)
> +#define CMD_WRITEBIT(2)
> +#define CMD_READ BIT(1)
> +#define CMD_VALIDBIT(0)
> +
> +#define  LS1X_NAND_TIMEOUT   20
> +
> +/* macros for registers read/write */
> +#define nand_readl(nandc, off)   \
> + readl((nandc)->reg_base + (off))
> +
> +#define nand_writel(nandc, off, val) \
> + writel((val), (nandc)->reg_base + (off))
> +
> +#define set_cmd(nandc, ctrl) \
> + nand_writel(nandc, NAND_CMD, ctrl)
> +
> +#define start_nand(nandc)\
> + nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
> +
> +struct ls1x_nand_chip {
> + struct nand_chip chip;
> + struct plat_ls1x_nand *pdata;
> +};
> +
> +struct ls1x_nand_controller {
> + struct clk *clk;
> + void __iomem *reg_base;
> +
> + int cmd_ctrl;
> + char datareg[8];
> + char *data_ptr;
> +
> + /* DMA stuff */
> + unsigned char *dma_buf;
> + unsigned int buf_off;
> + unsigned int buf_len;
> +
> + /* DMA Engine stuff */
> + unsigned int dma_chan_id;
> + struct dma_chan *dma_chan;
> + dma_cookie_t dma_cookie;
> + struct completion dma_complete;
> + void __iomem *dma_desc;
> +};
> +
> +static

Re: [PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Boris Brezillon 
Hi Kelvin,

On Sat, 28 May 2016 17:54:10 +0800
Keguang Zhang  wrote:

> From: Kelvin Cheung 
> 
> This patch adds NAND driver for Loongson1B.

I think your controller matches Mychaela's "high-level NAND controller"
definition [1]. Mychaela, can you confirm the Loongson controller
looks like yours?

I'll do a detailed review of the code soon.

Thanks,

Boris

[1]http://thread.gmane.org/gmane.linux.drivers.mtd/67346

> 
> Signed-off-by: Kelvin Cheung 
> 
> ---
> v3:
>Replace __raw_readl/__raw_writel with readl/writel.
>Split ls1x_nand into two structures: ls1x_nand_chip and 
> ls1x_nand_controller.
> V2:
>Modify the dependency in Kconfig due to the changes of DMA module.
> ---
>  drivers/mtd/nand/Kconfig  |   8 +
>  drivers/mtd/nand/Makefile |   1 +
>  drivers/mtd/nand/loongson1_nand.c | 555 
> ++
>  3 files changed, 564 insertions(+)
>  create mode 100644 drivers/mtd/nand/loongson1_nand.c
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index f05e0e9..be20fb8 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -563,4 +563,12 @@ config MTD_NAND_QCOM
> Enables support for NAND flash chips on SoCs containing the EBI2 NAND
> controller. This controller is found on IPQ806x SoC.
>  
> +config MTD_NAND_LOONGSON1
> + tristate "Support for Loongson1 SoC NAND controller"
> + depends on MACH_LOONGSON32
> + select DMADEVICES
> + select LOONGSON1_DMA
> + help
> + Enables support for NAND Flash on Loongson1 SoC based boards.
> +
>  endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index f553353..0310c0b 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)+= sunxi_nand.o
>  obj-$(CONFIG_MTD_NAND_HISI504)   += hisi504_nand.o
>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
> +obj-$(CONFIG_MTD_NAND_LOONGSON1) += loongson1_nand.o
>  
>  nand-objs := nand_base.o nand_bbt.o nand_timings.o
> diff --git a/drivers/mtd/nand/loongson1_nand.c 
> b/drivers/mtd/nand/loongson1_nand.c
> new file mode 100644
> index 000..86831773
> --- /dev/null
> +++ b/drivers/mtd/nand/loongson1_nand.c
> @@ -0,0 +1,555 @@
> +/*
> + * NAND Flash Driver for Loongson 1 SoC
> + *
> + * Copyright (C) 2015-2016 Zhang, Keguang 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/* Loongson 1 NAND Register Definitions */
> +#define NAND_CMD 0x0
> +#define NAND_ADDRL   0x4
> +#define NAND_ADDRH   0x8
> +#define NAND_TIMING  0xc
> +#define NAND_IDL 0x10
> +#define NAND_IDH 0x14
> +#define NAND_STATUS  0x14
> +#define NAND_PARAM   0x18
> +#define NAND_OP_NUM  0x1c
> +#define NAND_CS_RDY  0x20
> +
> +#define NAND_DMA_ADDR0x40
> +
> +/* NAND Command Register Bits */
> +#define OP_DONE  BIT(10)
> +#define OP_SPARE BIT(9)
> +#define OP_MAIN  BIT(8)
> +#define CMD_STATUS   BIT(7)
> +#define CMD_RESETBIT(6)
> +#define CMD_READID   BIT(5)
> +#define BLOCKS_ERASE BIT(4)
> +#define CMD_ERASEBIT(3)
> +#define CMD_WRITEBIT(2)
> +#define CMD_READ BIT(1)
> +#define CMD_VALIDBIT(0)
> +
> +#define  LS1X_NAND_TIMEOUT   20
> +
> +/* macros for registers read/write */
> +#define nand_readl(nandc, off)   \
> + readl((nandc)->reg_base + (off))
> +
> +#define nand_writel(nandc, off, val) \
> + writel((val), (nandc)->reg_base + (off))
> +
> +#define set_cmd(nandc, ctrl) \
> + nand_writel(nandc, NAND_CMD, ctrl)
> +
> +#define start_nand(nandc)\
> + nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
> +
> +struct ls1x_nand_chip {
> + struct nand_chip chip;
> + struct plat_ls1x_nand *pdata;
> +};
> +
> +struct ls1x_nand_controller {
> + struct clk *clk;
> + void __iomem *reg_base;
> +
> + int cmd_ctrl;
> + char datareg[8];
> + char *data_ptr;
> +
> + /* DMA stuff */
> + unsigned char *dma_buf;
> + unsigned int buf_off;
> + unsigned int buf_len;
> +
> + /* DMA Engine stuff */
> + unsigned int dma_chan_id;
> + struct dma_chan *dma_chan;
> + dma_cookie_t dma_cookie;
> + struct completion dma_complete;
> + void __iomem *dma_desc;
> +};
> +
> +static inline struct ls1x_nand_chip *to_ls1x_nand_chip(struct mtd_info *mtd)
> +{
> + return

[PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Keguang Zhang 
From: Kelvin Cheung 

This patch adds NAND driver for Loongson1B.

Signed-off-by: Kelvin Cheung 

---
v3:
   Replace __raw_readl/__raw_writel with readl/writel.
   Split ls1x_nand into two structures: ls1x_nand_chip and ls1x_nand_controller.
V2:
   Modify the dependency in Kconfig due to the changes of DMA module.
---
 drivers/mtd/nand/Kconfig  |   8 +
 drivers/mtd/nand/Makefile |   1 +
 drivers/mtd/nand/loongson1_nand.c | 555 ++
 3 files changed, 564 insertions(+)
 create mode 100644 drivers/mtd/nand/loongson1_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index f05e0e9..be20fb8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -563,4 +563,12 @@ config MTD_NAND_QCOM
  Enables support for NAND flash chips on SoCs containing the EBI2 NAND
  controller. This controller is found on IPQ806x SoC.
 
+config MTD_NAND_LOONGSON1
+   tristate "Support for Loongson1 SoC NAND controller"
+   depends on MACH_LOONGSON32
+   select DMADEVICES
+   select LOONGSON1_DMA
+   help
+   Enables support for NAND Flash on Loongson1 SoC based boards.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f553353..0310c0b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)  += sunxi_nand.o
 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
+obj-$(CONFIG_MTD_NAND_LOONGSON1)   += loongson1_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/loongson1_nand.c 
b/drivers/mtd/nand/loongson1_nand.c
new file mode 100644
index 000..86831773
--- /dev/null
+++ b/drivers/mtd/nand/loongson1_nand.c
@@ -0,0 +1,555 @@
+/*
+ * NAND Flash Driver for Loongson 1 SoC
+ *
+ * Copyright (C) 2015-2016 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* Loongson 1 NAND Register Definitions */
+#define NAND_CMD   0x0
+#define NAND_ADDRL 0x4
+#define NAND_ADDRH 0x8
+#define NAND_TIMING0xc
+#define NAND_IDL   0x10
+#define NAND_IDH   0x14
+#define NAND_STATUS0x14
+#define NAND_PARAM 0x18
+#define NAND_OP_NUM0x1c
+#define NAND_CS_RDY0x20
+
+#define NAND_DMA_ADDR  0x40
+
+/* NAND Command Register Bits */
+#define OP_DONEBIT(10)
+#define OP_SPARE   BIT(9)
+#define OP_MAINBIT(8)
+#define CMD_STATUS BIT(7)
+#define CMD_RESET  BIT(6)
+#define CMD_READID BIT(5)
+#define BLOCKS_ERASE   BIT(4)
+#define CMD_ERASE  BIT(3)
+#define CMD_WRITE  BIT(2)
+#define CMD_READ   BIT(1)
+#define CMD_VALID  BIT(0)
+
+#defineLS1X_NAND_TIMEOUT   20
+
+/* macros for registers read/write */
+#define nand_readl(nandc, off) \
+   readl((nandc)->reg_base + (off))
+
+#define nand_writel(nandc, off, val)   \
+   writel((val), (nandc)->reg_base + (off))
+
+#define set_cmd(nandc, ctrl)   \
+   nand_writel(nandc, NAND_CMD, ctrl)
+
+#define start_nand(nandc)  \
+   nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
+
+struct ls1x_nand_chip {
+   struct nand_chip chip;
+   struct plat_ls1x_nand *pdata;
+};
+
+struct ls1x_nand_controller {
+   struct clk *clk;
+   void __iomem *reg_base;
+
+   int cmd_ctrl;
+   char datareg[8];
+   char *data_ptr;
+
+   /* DMA stuff */
+   unsigned char *dma_buf;
+   unsigned int buf_off;
+   unsigned int buf_len;
+
+   /* DMA Engine stuff */
+   unsigned int dma_chan_id;
+   struct dma_chan *dma_chan;
+   dma_cookie_t dma_cookie;
+   struct completion dma_complete;
+   void __iomem *dma_desc;
+};
+
+static inline struct ls1x_nand_chip *to_ls1x_nand_chip(struct mtd_info *mtd)
+{
+   return container_of(mtd_to_nand(mtd), struct ls1x_nand_chip, chip);
+}
+
+static void dma_callback(void *data)
+{
+   struct mtd_info *mtd = (struct mtd_info *)data;
+   struct nand_chip *chip = mtd_to_nand(mtd);
+   struct ls1x_nand_controller *nandc = nand_get_controller_data(chip);
+   struct dma_tx_state state;
+   enum dma_status status;
+
+   status =
+   dmaengine_tx_status(nandc->dma_chan, nandc->dma_cookie, );
+   if (likely(status ==

[PATCH V3] mtd: nand: add Loongson1 NAND driver

2016-05-28 Thread Keguang Zhang 
From: Kelvin Cheung 

This patch adds NAND driver for Loongson1B.

Signed-off-by: Kelvin Cheung 

---
v3:
   Replace __raw_readl/__raw_writel with readl/writel.
   Split ls1x_nand into two structures: ls1x_nand_chip and ls1x_nand_controller.
V2:
   Modify the dependency in Kconfig due to the changes of DMA module.
---
 drivers/mtd/nand/Kconfig  |   8 +
 drivers/mtd/nand/Makefile |   1 +
 drivers/mtd/nand/loongson1_nand.c | 555 ++
 3 files changed, 564 insertions(+)
 create mode 100644 drivers/mtd/nand/loongson1_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index f05e0e9..be20fb8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -563,4 +563,12 @@ config MTD_NAND_QCOM
  Enables support for NAND flash chips on SoCs containing the EBI2 NAND
  controller. This controller is found on IPQ806x SoC.
 
+config MTD_NAND_LOONGSON1
+   tristate "Support for Loongson1 SoC NAND controller"
+   depends on MACH_LOONGSON32
+   select DMADEVICES
+   select LOONGSON1_DMA
+   help
+   Enables support for NAND Flash on Loongson1 SoC based boards.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f553353..0310c0b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI)  += sunxi_nand.o
 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
+obj-$(CONFIG_MTD_NAND_LOONGSON1)   += loongson1_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/drivers/mtd/nand/loongson1_nand.c 
b/drivers/mtd/nand/loongson1_nand.c
new file mode 100644
index 000..86831773
--- /dev/null
+++ b/drivers/mtd/nand/loongson1_nand.c
@@ -0,0 +1,555 @@
+/*
+ * NAND Flash Driver for Loongson 1 SoC
+ *
+ * Copyright (C) 2015-2016 Zhang, Keguang 
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/* Loongson 1 NAND Register Definitions */
+#define NAND_CMD   0x0
+#define NAND_ADDRL 0x4
+#define NAND_ADDRH 0x8
+#define NAND_TIMING0xc
+#define NAND_IDL   0x10
+#define NAND_IDH   0x14
+#define NAND_STATUS0x14
+#define NAND_PARAM 0x18
+#define NAND_OP_NUM0x1c
+#define NAND_CS_RDY0x20
+
+#define NAND_DMA_ADDR  0x40
+
+/* NAND Command Register Bits */
+#define OP_DONEBIT(10)
+#define OP_SPARE   BIT(9)
+#define OP_MAINBIT(8)
+#define CMD_STATUS BIT(7)
+#define CMD_RESET  BIT(6)
+#define CMD_READID BIT(5)
+#define BLOCKS_ERASE   BIT(4)
+#define CMD_ERASE  BIT(3)
+#define CMD_WRITE  BIT(2)
+#define CMD_READ   BIT(1)
+#define CMD_VALID  BIT(0)
+
+#defineLS1X_NAND_TIMEOUT   20
+
+/* macros for registers read/write */
+#define nand_readl(nandc, off) \
+   readl((nandc)->reg_base + (off))
+
+#define nand_writel(nandc, off, val)   \
+   writel((val), (nandc)->reg_base + (off))
+
+#define set_cmd(nandc, ctrl)   \
+   nand_writel(nandc, NAND_CMD, ctrl)
+
+#define start_nand(nandc)  \
+   nand_writel(nandc, NAND_CMD, nand_readl(nandc, NAND_CMD) | CMD_VALID)
+
+struct ls1x_nand_chip {
+   struct nand_chip chip;
+   struct plat_ls1x_nand *pdata;
+};
+
+struct ls1x_nand_controller {
+   struct clk *clk;
+   void __iomem *reg_base;
+
+   int cmd_ctrl;
+   char datareg[8];
+   char *data_ptr;
+
+   /* DMA stuff */
+   unsigned char *dma_buf;
+   unsigned int buf_off;
+   unsigned int buf_len;
+
+   /* DMA Engine stuff */
+   unsigned int dma_chan_id;
+   struct dma_chan *dma_chan;
+   dma_cookie_t dma_cookie;
+   struct completion dma_complete;
+   void __iomem *dma_desc;
+};
+
+static inline struct ls1x_nand_chip *to_ls1x_nand_chip(struct mtd_info *mtd)
+{
+   return container_of(mtd_to_nand(mtd), struct ls1x_nand_chip, chip);
+}
+
+static void dma_callback(void *data)
+{
+   struct mtd_info *mtd = (struct mtd_info *)data;
+   struct nand_chip *chip = mtd_to_nand(mtd);
+   struct ls1x_nand_controller *nandc = nand_get_controller_data(chip);
+   struct dma_tx_state state;
+   enum dma_status status;
+
+   status =
+   dmaengine_tx_status(nandc->dma_chan, nandc->dma_cookie, );
+   if (likely(status == DMA_COMPLETE))
+   dev_dbg(mtd->dev.parent, "DMA complete with cookie=%d\n",