[PATCH V4 15/25] mmc: mmci: add variant properties to define cpsm & cmdresp bits

2018-10-02 Thread Ludovic Barre 
From: Ludovic Barre 

This patch adds command variant properties to define
cpsm enable bit and responses.
Needed to support the STM32 variant (shift of cpsm bit,
specific definition of commands response).

Signed-off-by: Ludovic Barre 
---
 drivers/mmc/host/mmci.c | 47 +++
 drivers/mmc/host/mmci.h |  8 
 2 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 168bb6d..00a9244 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -50,6 +50,10 @@ static unsigned int fmax = 515633;
 static struct variant_data variant_arm = {
.fifosize   = 16 * 4,
.fifohalfsize   = 8 * 4,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -64,6 +68,10 @@ static struct variant_data variant_arm = {
 static struct variant_data variant_arm_extended_fifo = {
.fifosize   = 128 * 4,
.fifohalfsize   = 64 * 4,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -78,6 +86,10 @@ static struct variant_data variant_arm_extended_fifo_hwfc = {
.fifosize   = 128 * 4,
.fifohalfsize   = 64 * 4,
.clkreg_enable  = MCI_ARM_HWFCEN,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -93,6 +105,10 @@ static struct variant_data variant_u300 = {
.fifohalfsize   = 8 * 4,
.clkreg_enable  = MCI_ST_U300_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -113,6 +129,10 @@ static struct variant_data variant_nomadik = {
.fifohalfsize   = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -136,6 +156,10 @@ static struct variant_data variant_ux500 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -163,6 +187,10 @@ static struct variant_data variant_ux500v2 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datactrl_mask_ddrmode  = MCI_DPSM_ST_DDRMODE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
@@ -192,6 +220,10 @@ static struct variant_data variant_stm32 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,

[PATCH V4 15/25] mmc: mmci: add variant properties to define cpsm & cmdresp bits

2018-10-02 Thread Ludovic Barre 
From: Ludovic Barre 

This patch adds command variant properties to define
cpsm enable bit and responses.
Needed to support the STM32 variant (shift of cpsm bit,
specific definition of commands response).

Signed-off-by: Ludovic Barre 
---
 drivers/mmc/host/mmci.c | 47 +++
 drivers/mmc/host/mmci.h |  8 
 2 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 168bb6d..00a9244 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -50,6 +50,10 @@ static unsigned int fmax = 515633;
 static struct variant_data variant_arm = {
.fifosize   = 16 * 4,
.fifohalfsize   = 8 * 4,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -64,6 +68,10 @@ static struct variant_data variant_arm = {
 static struct variant_data variant_arm_extended_fifo = {
.fifosize   = 128 * 4,
.fifohalfsize   = 64 * 4,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -78,6 +86,10 @@ static struct variant_data variant_arm_extended_fifo_hwfc = {
.fifosize   = 128 * 4,
.fifohalfsize   = 64 * 4,
.clkreg_enable  = MCI_ARM_HWFCEN,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.pwrreg_powerup = MCI_PWR_UP,
@@ -93,6 +105,10 @@ static struct variant_data variant_u300 = {
.fifohalfsize   = 8 * 4,
.clkreg_enable  = MCI_ST_U300_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 16,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -113,6 +129,10 @@ static struct variant_data variant_nomadik = {
.fifohalfsize   = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -136,6 +156,10 @@ static struct variant_data variant_ux500 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
.datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
@@ -163,6 +187,10 @@ static struct variant_data variant_ux500v2 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,
.datactrl_mask_ddrmode  = MCI_DPSM_ST_DDRMODE,
.datalength_bits= 24,
.datactrl_blocksz   = 11,
@@ -192,6 +220,10 @@ static struct variant_data variant_stm32 = {
.clkreg_enable  = MCI_ST_UX500_HWFCEN,
.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
.clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+   .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
+   .cmdreg_lrsp_crc= MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
+   .cmdreg_srsp_crc= MCI_CPSM_RESPONSE,
+   .cmdreg_srsp= MCI_CPSM_RESPONSE,