subject:"\[PATCH V4 3\/3\] mmc\: tegra\: SDMMC pads auto\-calibration"

Re: [PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

2019-01-21 Thread Ulf Hansson

On Thu, 10 Jan 2019 at 23:46, Sowjanya Komatineni
 wrote:
>
> Program initial drive code offsets which will be used by auto
> calibration process.
>
> Program fixed drive strengths for SDMMC pads in pad control
> register when auto cal timeouts.
> Fixed settings are based on Pre-SI analysis of the pad design.
>
> Signed-off-by: Sowjanya Komatineni 

Applied for next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-tegra.c | 160 
> ++---
>  1 file changed, 119 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index e6ace31e2a41..7d681a8fa4ba 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -75,6 +75,7 @@
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK   0x000f
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL0x7
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD  BIT(31)
> +#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
>
>  #define SDHCI_TEGRA_AUTO_CAL_STATUS0x1ec
>  #define SDHCI_TEGRA_AUTO_CAL_ACTIVEBIT(31)
> @@ -121,6 +122,8 @@ struct sdhci_tegra {
> struct pinctrl *pinctrl_sdmmc;
> struct pinctrl_state *pinctrl_state_3v3;
> struct pinctrl_state *pinctrl_state_1v8;
> +   struct pinctrl_state *pinctrl_state_3v3_drv;
> +   struct pinctrl_state *pinctrl_state_1v8_drv;
>
> struct sdhci_tegra_autocal_offsets autocal_offsets;
> ktime_t last_calib;
> @@ -411,6 +414,76 @@ static void tegra_sdhci_set_pad_autocal_offset(struct 
> sdhci_host *host,
> sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  }
>
> +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
> +  bool state_drvupdn)
> +{
> +   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +   struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> +   struct sdhci_tegra_autocal_offsets *offsets =
> +   _host->autocal_offsets;
> +   struct pinctrl_state *pinctrl_drvupdn = NULL;
> +   int ret = 0;
> +   u8 drvup = 0, drvdn = 0;
> +   u32 reg;
> +
> +   if (!state_drvupdn) {
> +   /* PADS Drive Strength */
> +   if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +   if (tegra_host->pinctrl_state_1v8_drv) {
> +   pinctrl_drvupdn =
> +   tegra_host->pinctrl_state_1v8_drv;
> +   } else {
> +   drvup = offsets->pull_up_1v8_timeout;
> +   drvdn = offsets->pull_down_1v8_timeout;
> +   }
> +   } else {
> +   if (tegra_host->pinctrl_state_3v3_drv) {
> +   pinctrl_drvupdn =
> +   tegra_host->pinctrl_state_3v3_drv;
> +   } else {
> +   drvup = offsets->pull_up_3v3_timeout;
> +   drvdn = offsets->pull_down_3v3_timeout;
> +   }
> +   }
> +
> +   if (pinctrl_drvupdn != NULL) {
> +   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +   pinctrl_drvupdn);
> +   if (ret < 0)
> +   dev_err(mmc_dev(host->mmc),
> +   "failed pads drvupdn, ret: %d\n", 
> ret);
> +   } else if ((drvup) || (drvdn)) {
> +   reg = sdhci_readl(host,
> +   SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +   reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
> +   reg |= (drvup << 20) | (drvdn << 12);
> +   sdhci_writel(host, reg,
> +   SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> +   }
> +
> +   } else {
> +   /* Dual Voltage PADS Voltage selection */
> +   if (!tegra_host->pad_control_available)
> +   return 0;
> +
> +   if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> +   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +   
> tegra_host->pinctrl_state_1v8);
> +   if (ret < 0)
> +   dev_err(mmc_dev(host->mmc),
> +   "setting 1.8V failed, ret: %d\n", 
> ret);
> +   } else {
> +   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> +   
> tegra_host->pinctrl_state_3v3);
> +   if (ret < 0)
> +   dev_err(mmc_dev(host->mmc),
>

Re: [PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

2019-01-14 Thread Adrian Hunter

On 11/01/19 12:46 AM, Sowjanya Komatineni wrote:
> Program initial drive code offsets which will be used by auto
> calibration process.
> 
> Program fixed drive strengths for SDMMC pads in pad control
> register when auto cal timeouts.
> Fixed settings are based on Pre-SI analysis of the pad design.
> 
> Signed-off-by: Sowjanya Komatineni 

Acked-by: Adrian Hunter 

> ---
>  drivers/mmc/host/sdhci-tegra.c | 160 
> ++---
>  1 file changed, 119 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index e6ace31e2a41..7d681a8fa4ba 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -75,6 +75,7 @@
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x000f
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL  0x7
>  #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRDBIT(31)
> +#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK   0x07FFF000
>  
>  #define SDHCI_TEGRA_AUTO_CAL_STATUS  0x1ec
>  #define SDHCI_TEGRA_AUTO_CAL_ACTIVE  BIT(31)
> @@ -121,6 +122,8 @@ struct sdhci_tegra {
>   struct pinctrl *pinctrl_sdmmc;
>   struct pinctrl_state *pinctrl_state_3v3;
>   struct pinctrl_state *pinctrl_state_1v8;
> + struct pinctrl_state *pinctrl_state_3v3_drv;
> + struct pinctrl_state *pinctrl_state_1v8_drv;
>  
>   struct sdhci_tegra_autocal_offsets autocal_offsets;
>   ktime_t last_calib;
> @@ -411,6 +414,76 @@ static void tegra_sdhci_set_pad_autocal_offset(struct 
> sdhci_host *host,
>   sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
>  }
>  
> +static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
> +bool state_drvupdn)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
> + struct sdhci_tegra_autocal_offsets *offsets =
> + _host->autocal_offsets;
> + struct pinctrl_state *pinctrl_drvupdn = NULL;
> + int ret = 0;
> + u8 drvup = 0, drvdn = 0;
> + u32 reg;
> +
> + if (!state_drvupdn) {
> + /* PADS Drive Strength */
> + if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> + if (tegra_host->pinctrl_state_1v8_drv) {
> + pinctrl_drvupdn =
> + tegra_host->pinctrl_state_1v8_drv;
> + } else {
> + drvup = offsets->pull_up_1v8_timeout;
> + drvdn = offsets->pull_down_1v8_timeout;
> + }
> + } else {
> + if (tegra_host->pinctrl_state_3v3_drv) {
> + pinctrl_drvupdn =
> + tegra_host->pinctrl_state_3v3_drv;
> + } else {
> + drvup = offsets->pull_up_3v3_timeout;
> + drvdn = offsets->pull_down_3v3_timeout;
> + }
> + }
> +
> + if (pinctrl_drvupdn != NULL) {
> + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> + pinctrl_drvupdn);
> + if (ret < 0)
> + dev_err(mmc_dev(host->mmc),
> + "failed pads drvupdn, ret: %d\n", ret);
> + } else if ((drvup) || (drvdn)) {
> + reg = sdhci_readl(host,
> + SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> + reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
> + reg |= (drvup << 20) | (drvdn << 12);
> + sdhci_writel(host, reg,
> + SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
> + }
> +
> + } else {
> + /* Dual Voltage PADS Voltage selection */
> + if (!tegra_host->pad_control_available)
> + return 0;
> +
> + if (voltage == MMC_SIGNAL_VOLTAGE_180) {
> + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> + tegra_host->pinctrl_state_1v8);
> + if (ret < 0)
> + dev_err(mmc_dev(host->mmc),
> + "setting 1.8V failed, ret: %d\n", ret);
> + } else {
> + ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
> + tegra_host->pinctrl_state_3v3);
> + if (ret < 0)
> + dev_err(mmc_dev(host->mmc),
> + "setting 3.3V failed, ret: %d\n", ret);
> + }
> + }
> +
> + return ret;
> +}
> +
>  static void

[PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

2019-01-10 Thread Sowjanya Komatineni

Program initial drive code offsets which will be used by auto
calibration process.

Program fixed drive strengths for SDMMC pads in pad control
register when auto cal timeouts.
Fixed settings are based on Pre-SI analysis of the pad design.

Signed-off-by: Sowjanya Komatineni 
---
 drivers/mmc/host/sdhci-tegra.c | 160 ++---
 1 file changed, 119 insertions(+), 41 deletions(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index e6ace31e2a41..7d681a8fa4ba 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -75,6 +75,7 @@
 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK   0x000f
 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL0x7
 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD  BIT(31)
+#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
 
 #define SDHCI_TEGRA_AUTO_CAL_STATUS0x1ec
 #define SDHCI_TEGRA_AUTO_CAL_ACTIVEBIT(31)
@@ -121,6 +122,8 @@ struct sdhci_tegra {
struct pinctrl *pinctrl_sdmmc;
struct pinctrl_state *pinctrl_state_3v3;
struct pinctrl_state *pinctrl_state_1v8;
+   struct pinctrl_state *pinctrl_state_3v3_drv;
+   struct pinctrl_state *pinctrl_state_1v8_drv;
 
struct sdhci_tegra_autocal_offsets autocal_offsets;
ktime_t last_calib;
@@ -411,6 +414,76 @@ static void tegra_sdhci_set_pad_autocal_offset(struct 
sdhci_host *host,
sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
 }
 
+static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
+  bool state_drvupdn)
+{
+   struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+   struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+   struct sdhci_tegra_autocal_offsets *offsets =
+   _host->autocal_offsets;
+   struct pinctrl_state *pinctrl_drvupdn = NULL;
+   int ret = 0;
+   u8 drvup = 0, drvdn = 0;
+   u32 reg;
+
+   if (!state_drvupdn) {
+   /* PADS Drive Strength */
+   if (voltage == MMC_SIGNAL_VOLTAGE_180) {
+   if (tegra_host->pinctrl_state_1v8_drv) {
+   pinctrl_drvupdn =
+   tegra_host->pinctrl_state_1v8_drv;
+   } else {
+   drvup = offsets->pull_up_1v8_timeout;
+   drvdn = offsets->pull_down_1v8_timeout;
+   }
+   } else {
+   if (tegra_host->pinctrl_state_3v3_drv) {
+   pinctrl_drvupdn =
+   tegra_host->pinctrl_state_3v3_drv;
+   } else {
+   drvup = offsets->pull_up_3v3_timeout;
+   drvdn = offsets->pull_down_3v3_timeout;
+   }
+   }
+
+   if (pinctrl_drvupdn != NULL) {
+   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+   pinctrl_drvupdn);
+   if (ret < 0)
+   dev_err(mmc_dev(host->mmc),
+   "failed pads drvupdn, ret: %d\n", ret);
+   } else if ((drvup) || (drvdn)) {
+   reg = sdhci_readl(host,
+   SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
+   reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
+   reg |= (drvup << 20) | (drvdn << 12);
+   sdhci_writel(host, reg,
+   SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
+   }
+
+   } else {
+   /* Dual Voltage PADS Voltage selection */
+   if (!tegra_host->pad_control_available)
+   return 0;
+
+   if (voltage == MMC_SIGNAL_VOLTAGE_180) {
+   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+   tegra_host->pinctrl_state_1v8);
+   if (ret < 0)
+   dev_err(mmc_dev(host->mmc),
+   "setting 1.8V failed, ret: %d\n", ret);
+   } else {
+   ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+   tegra_host->pinctrl_state_3v3);
+   if (ret < 0)
+   dev_err(mmc_dev(host->mmc),
+   "setting 3.3V failed, ret: %d\n", ret);
+   }
+   }
+
+   return ret;
+}
+
 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
 {
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -437,6 +510,7 @@ static void

Re: [PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

Re: [PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

[PATCH V4 3/3] mmc: tegra: SDMMC pads auto-calibration

3 matches

Site Navigation

Mail list logo

Footer information