Re: [PATCH V8 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support

2019-09-10 Thread Ben Chuang 
On Wed, Sep 11, 2019 at 12:42 PM Guenter Roeck  wrote:
>
> On Fri, Sep 06, 2019 at 10:33:26AM +0800, Ben Chuang wrote:
> > From: Ben Chuang 
> >
> > Add support for the GL9750 and GL9755 chipsets.
> >
> > Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/
> > GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor
> > tuning flow for GL9750.
> >
> > Co-developed-by: Michael K Johnson 
> > Signed-off-by: Michael K Johnson 
> > Signed-off-by: Ben Chuang 
> > ---
> >  drivers/mmc/host/Kconfig  |   1 +
> >  drivers/mmc/host/Makefile |   2 +-
> >  drivers/mmc/host/sdhci-pci-core.c |   2 +
> >  drivers/mmc/host/sdhci-pci-gli.c  | 355 ++
> >  drivers/mmc/host/sdhci-pci.h  |   5 +
> >  5 files changed, 364 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/mmc/host/sdhci-pci-gli.c
> >
> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> > index 931770f17087..9fbfff514d6c 100644
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -94,6 +94,7 @@ config MMC_SDHCI_PCI
> >   depends on MMC_SDHCI && PCI
> >   select MMC_CQHCI
> >   select IOSF_MBI if X86
> > + select MMC_SDHCI_IO_ACCESSORS
> >   help
> > This selects the PCI Secure Digital Host Controller Interface.
> > Most controllers found today are PCI devices.
> > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> > index 73578718f119..661445415090 100644
> > --- a/drivers/mmc/host/Makefile
> > +++ b/drivers/mmc/host/Makefile
> > @@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS)   += mxs-mmc.o
> >  obj-$(CONFIG_MMC_SDHCI)  += sdhci.o
> >  obj-$(CONFIG_MMC_SDHCI_PCI)  += sdhci-pci.o
> >  sdhci-pci-y  += sdhci-pci-core.o sdhci-pci-o2micro.o 
> > sdhci-pci-arasan.o \
> > -sdhci-pci-dwc-mshc.o
> > +sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
> >  obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o
> >  obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
> >  obj-$(CONFIG_MMC_SDHCI_PXAV3)+= sdhci-pxav3.o
> > diff --git a/drivers/mmc/host/sdhci-pci-core.c 
> > b/drivers/mmc/host/sdhci-pci-core.c
> > index 4154ee11b47d..e5835fbf73bc 100644
> > --- a/drivers/mmc/host/sdhci-pci-core.c
> > +++ b/drivers/mmc/host/sdhci-pci-core.c
> > @@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = {
> >   SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
> >   SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
> >   SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
> > + SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
> > + SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
> >   SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
> >   /* Generic SD host controller */
> >   {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c 
> > b/drivers/mmc/host/sdhci-pci-gli.c
> > new file mode 100644
> > index ..94462b94abec
> > --- /dev/null
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -0,0 +1,355 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2019 Genesys Logic, Inc.
> > + *
> > + * Authors: Ben Chuang 
> > + *
> > + * Version: v0.9.0 (2019-08-08)
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include "sdhci.h"
> > +#include "sdhci-pci.h"
> > +
> > +/*  Genesys Logic extra registers */
> > +#define SDHCI_GLI_9750_WT 0x800
> > +#define   SDHCI_GLI_9750_WT_EN  BIT(0)
> > +#define   GLI_9750_WT_EN_ON  0x1
> > +#define   GLI_9750_WT_EN_OFF 0x0
> > +
> > +#define SDHCI_GLI_9750_DRIVING  0x860
> > +#define   SDHCI_GLI_9750_DRIVING_1GENMASK(11, 0)
> > +#define   SDHCI_GLI_9750_DRIVING_2GENMASK(27, 26)
> > +#define   GLI_9750_DRIVING_1_VALUE0xFFF
> > +#define   GLI_9750_DRIVING_2_VALUE0x3
> > +
> > +#define SDHCI_GLI_9750_PLL 0x864
> > +#define   SDHCI_GLI_9750_PLL_TX2_INVBIT(23)
> > +#define   SDHCI_GLI_9750_PLL_TX2_DLYGENMASK(22, 20)
> > +#define   GLI_9750_PLL_TX2_INV_VALUE0x1
> > +#define   GLI_9750_PLL_TX2_DLY_VALUE0x0
> > +
> > +#define SDHCI_GLI_9750_SW_CTRL  0x874
> > +#define   SDHCI_GLI_9750_SW_CTRL_4GENMASK(7, 6)
> > +#define   GLI_9750_SW_CTRL_4_VALUE0x3
> > +
> > +#define SDHCI_GLI_9750_MISC0x878
> > +#define   SDHCI_GLI_9750_MISC_TX1_INVBIT(2)
> > +#define   SDHCI_GLI_9750_MISC_RX_INV BIT(3)
> > +#define   SDHCI_GLI_9750_MISC_TX1_DLYGENMASK(6, 4)
> > +#define   GLI_9750_MISC_TX1_INV_VALUE0x0
> > +#define   GLI_9750_MISC_RX_INV_ON0x1
> > +#define   GLI_9750_MISC_RX_INV_OFF   0x0
> > +#define   GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
> > +#define   GLI_9750_MISC_TX1_DLY_VALUE0x5
> > +
> > +#define SDHCI_GLI_9750_TUNING_CONTROL  0x540
> > +#define   SDHCI_GLI_9750_TUNING_CONTROL_EN  BIT(4)
> > +#define

Re: [PATCH V8 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support

2019-09-10 Thread Guenter Roeck 
On Fri, Sep 06, 2019 at 10:33:26AM +0800, Ben Chuang wrote:
> From: Ben Chuang 
> 
> Add support for the GL9750 and GL9755 chipsets.
> 
> Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/
> GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor
> tuning flow for GL9750.
> 
> Co-developed-by: Michael K Johnson 
> Signed-off-by: Michael K Johnson 
> Signed-off-by: Ben Chuang 
> ---
>  drivers/mmc/host/Kconfig  |   1 +
>  drivers/mmc/host/Makefile |   2 +-
>  drivers/mmc/host/sdhci-pci-core.c |   2 +
>  drivers/mmc/host/sdhci-pci-gli.c  | 355 ++
>  drivers/mmc/host/sdhci-pci.h  |   5 +
>  5 files changed, 364 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/mmc/host/sdhci-pci-gli.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 931770f17087..9fbfff514d6c 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -94,6 +94,7 @@ config MMC_SDHCI_PCI
>   depends on MMC_SDHCI && PCI
>   select MMC_CQHCI
>   select IOSF_MBI if X86
> + select MMC_SDHCI_IO_ACCESSORS
>   help
> This selects the PCI Secure Digital Host Controller Interface.
> Most controllers found today are PCI devices.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 73578718f119..661445415090 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS)   += mxs-mmc.o
>  obj-$(CONFIG_MMC_SDHCI)  += sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_PCI)  += sdhci-pci.o
>  sdhci-pci-y  += sdhci-pci-core.o sdhci-pci-o2micro.o 
> sdhci-pci-arasan.o \
> -sdhci-pci-dwc-mshc.o
> +sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
>  obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o
>  obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
>  obj-$(CONFIG_MMC_SDHCI_PXAV3)+= sdhci-pxav3.o
> diff --git a/drivers/mmc/host/sdhci-pci-core.c 
> b/drivers/mmc/host/sdhci-pci-core.c
> index 4154ee11b47d..e5835fbf73bc 100644
> --- a/drivers/mmc/host/sdhci-pci-core.c
> +++ b/drivers/mmc/host/sdhci-pci-core.c
> @@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = {
>   SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
>   SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
>   SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
> + SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
> + SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
>   SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
>   /* Generic SD host controller */
>   {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c 
> b/drivers/mmc/host/sdhci-pci-gli.c
> new file mode 100644
> index ..94462b94abec
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -0,0 +1,355 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2019 Genesys Logic, Inc.
> + *
> + * Authors: Ben Chuang 
> + *
> + * Version: v0.9.0 (2019-08-08)
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "sdhci.h"
> +#include "sdhci-pci.h"
> +
> +/*  Genesys Logic extra registers */
> +#define SDHCI_GLI_9750_WT 0x800
> +#define   SDHCI_GLI_9750_WT_EN  BIT(0)
> +#define   GLI_9750_WT_EN_ON  0x1
> +#define   GLI_9750_WT_EN_OFF 0x0
> +
> +#define SDHCI_GLI_9750_DRIVING  0x860
> +#define   SDHCI_GLI_9750_DRIVING_1GENMASK(11, 0)
> +#define   SDHCI_GLI_9750_DRIVING_2GENMASK(27, 26)
> +#define   GLI_9750_DRIVING_1_VALUE0xFFF
> +#define   GLI_9750_DRIVING_2_VALUE0x3
> +
> +#define SDHCI_GLI_9750_PLL 0x864
> +#define   SDHCI_GLI_9750_PLL_TX2_INVBIT(23)
> +#define   SDHCI_GLI_9750_PLL_TX2_DLYGENMASK(22, 20)
> +#define   GLI_9750_PLL_TX2_INV_VALUE0x1
> +#define   GLI_9750_PLL_TX2_DLY_VALUE0x0
> +
> +#define SDHCI_GLI_9750_SW_CTRL  0x874
> +#define   SDHCI_GLI_9750_SW_CTRL_4GENMASK(7, 6)
> +#define   GLI_9750_SW_CTRL_4_VALUE0x3
> +
> +#define SDHCI_GLI_9750_MISC0x878
> +#define   SDHCI_GLI_9750_MISC_TX1_INVBIT(2)
> +#define   SDHCI_GLI_9750_MISC_RX_INV BIT(3)
> +#define   SDHCI_GLI_9750_MISC_TX1_DLYGENMASK(6, 4)
> +#define   GLI_9750_MISC_TX1_INV_VALUE0x0
> +#define   GLI_9750_MISC_RX_INV_ON0x1
> +#define   GLI_9750_MISC_RX_INV_OFF   0x0
> +#define   GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
> +#define   GLI_9750_MISC_TX1_DLY_VALUE0x5
> +
> +#define SDHCI_GLI_9750_TUNING_CONTROL  0x540
> +#define   SDHCI_GLI_9750_TUNING_CONTROL_EN  BIT(4)
> +#define   GLI_9750_TUNING_CONTROL_EN_ON 0x1
> +#define   GLI_9750_TUNING_CONTROL_EN_OFF0x0
> +#define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1BIT(16)
> +#define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2GENMASK(20, 19)
> +#define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE

[PATCH V8 5/5] mmc: host: sdhci-pci: Add Genesys Logic GL975x support

2019-09-05 Thread Ben Chuang 
From: Ben Chuang 

Add support for the GL9750 and GL9755 chipsets.

Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/
GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor
tuning flow for GL9750.

Co-developed-by: Michael K Johnson 
Signed-off-by: Michael K Johnson 
Signed-off-by: Ben Chuang 
---
 drivers/mmc/host/Kconfig  |   1 +
 drivers/mmc/host/Makefile |   2 +-
 drivers/mmc/host/sdhci-pci-core.c |   2 +
 drivers/mmc/host/sdhci-pci-gli.c  | 355 ++
 drivers/mmc/host/sdhci-pci.h  |   5 +
 5 files changed, 364 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mmc/host/sdhci-pci-gli.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 931770f17087..9fbfff514d6c 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -94,6 +94,7 @@ config MMC_SDHCI_PCI
depends on MMC_SDHCI && PCI
select MMC_CQHCI
select IOSF_MBI if X86
+   select MMC_SDHCI_IO_ACCESSORS
help
  This selects the PCI Secure Digital Host Controller Interface.
  Most controllers found today are PCI devices.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 73578718f119..661445415090 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
 obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PCI)+= sdhci-pci.o
 sdhci-pci-y+= sdhci-pci-core.o sdhci-pci-o2micro.o 
sdhci-pci-arasan.o \
-  sdhci-pci-dwc-mshc.o
+  sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
 obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI))   += sdhci-pci-data.o
 obj-$(CONFIG_MMC_SDHCI_ACPI)   += sdhci-acpi.o
 obj-$(CONFIG_MMC_SDHCI_PXAV3)  += sdhci-pxav3.o
diff --git a/drivers/mmc/host/sdhci-pci-core.c 
b/drivers/mmc/host/sdhci-pci-core.c
index 4154ee11b47d..e5835fbf73bc 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -1682,6 +1682,8 @@ static const struct pci_device_id pci_ids[] = {
SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
+   SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
+   SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
/* Generic SD host controller */
{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
new file mode 100644
index ..94462b94abec
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Genesys Logic, Inc.
+ *
+ * Authors: Ben Chuang 
+ *
+ * Version: v0.9.0 (2019-08-08)
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "sdhci.h"
+#include "sdhci-pci.h"
+
+/*  Genesys Logic extra registers */
+#define SDHCI_GLI_9750_WT 0x800
+#define   SDHCI_GLI_9750_WT_EN  BIT(0)
+#define   GLI_9750_WT_EN_ON0x1
+#define   GLI_9750_WT_EN_OFF   0x0
+
+#define SDHCI_GLI_9750_DRIVING  0x860
+#define   SDHCI_GLI_9750_DRIVING_1GENMASK(11, 0)
+#define   SDHCI_GLI_9750_DRIVING_2GENMASK(27, 26)
+#define   GLI_9750_DRIVING_1_VALUE0xFFF
+#define   GLI_9750_DRIVING_2_VALUE0x3
+
+#define SDHCI_GLI_9750_PLL   0x864
+#define   SDHCI_GLI_9750_PLL_TX2_INVBIT(23)
+#define   SDHCI_GLI_9750_PLL_TX2_DLYGENMASK(22, 20)
+#define   GLI_9750_PLL_TX2_INV_VALUE0x1
+#define   GLI_9750_PLL_TX2_DLY_VALUE0x0
+
+#define SDHCI_GLI_9750_SW_CTRL  0x874
+#define   SDHCI_GLI_9750_SW_CTRL_4GENMASK(7, 6)
+#define   GLI_9750_SW_CTRL_4_VALUE0x3
+
+#define SDHCI_GLI_9750_MISC0x878
+#define   SDHCI_GLI_9750_MISC_TX1_INVBIT(2)
+#define   SDHCI_GLI_9750_MISC_RX_INV BIT(3)
+#define   SDHCI_GLI_9750_MISC_TX1_DLYGENMASK(6, 4)
+#define   GLI_9750_MISC_TX1_INV_VALUE0x0
+#define   GLI_9750_MISC_RX_INV_ON0x1
+#define   GLI_9750_MISC_RX_INV_OFF   0x0
+#define   GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
+#define   GLI_9750_MISC_TX1_DLY_VALUE0x5
+
+#define SDHCI_GLI_9750_TUNING_CONTROL0x540
+#define   SDHCI_GLI_9750_TUNING_CONTROL_EN  BIT(4)
+#define   GLI_9750_TUNING_CONTROL_EN_ON 0x1
+#define   GLI_9750_TUNING_CONTROL_EN_OFF0x0
+#define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1BIT(16)
+#define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2GENMASK(20, 19)
+#define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE0x1
+#define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE0x2
+
+#define SDHCI_GLI_9750_TUNING_PARAMETERS   0x544
+#define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLYGENMASK(2, 0)
+#define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE0x1
+
+#define