Re: [PATCH v1 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-19 Thread Daniel Lezcano 
On 19/03/2021 12:24, Robert Foss wrote:
> On Fri, 19 Mar 2021 at 11:49, Robert Foss  wrote:
>>
>> sm8350 has 29 thermal sensors split across two tsens controllers. Add
>> the thermal zones to expose them and wireup the cpus to throttle their
>> frequencies on crossing passive temperature thresholds.
>>
>> Signed-off-by: Robert Foss 
>> ---

[ ... ]

>> +   };
>> +
>> +   // TODO: What is the NSP subsystem?
> 
> This comment should not have been included, will remove in v2

Please trim when replying to a large patch file.

[ ... ]

>> +   trips {
>> +   nspss1_alert0: trip-point0 {
>> +   temperature = <9>;
>> +   hysteresis = <1000>;
>> +   type = "hot";
>> +   };
>> +   };
>> +   };
>> +
>> +   // TODO: What is the NSP subsystem?
> 
> This comment should not have been included, will remove in v2

[ ... ]

>> +   trips {
>> +   nspss2_alert0: trip-point0 {
>> +   temperature = <9>;
>> +   hysteresis = <1000>;
>> +   type = "hot";
>> +   };
>> +   };
>> +   };
>> +
>> +   // TODO: What is the NSP subsystem?
> 
> This comment should not have been included, will remove in v2
> 

[ ... ]



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Re: [PATCH v1 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-19 Thread Robert Foss 
On Fri, 19 Mar 2021 at 11:49, Robert Foss  wrote:
>
> sm8350 has 29 thermal sensors split across two tsens controllers. Add
> the thermal zones to expose them and wireup the cpus to throttle their
> frequencies on crossing passive temperature thresholds.
>
> Signed-off-by: Robert Foss 
> ---
>  arch/arm64/boot/dts/qcom/sm8350.dtsi | 829 +++
>  1 file changed, 829 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
> b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 4abdba78cec1..424887652f47 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  / {
> interrupt-parent = <&intc>;
> @@ -46,6 +47,7 @@ CPU0: cpu@0 {
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> +   #cooling-cells = <2>;
> L2_0: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -62,6 +64,7 @@ CPU1: cpu@100 {
> enable-method = "psci";
> next-level-cache = <&L2_100>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> +   #cooling-cells = <2>;
> L2_100: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -75,6 +78,7 @@ CPU2: cpu@200 {
> enable-method = "psci";
> next-level-cache = <&L2_200>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> +   #cooling-cells = <2>;
> L2_200: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -88,6 +92,7 @@ CPU3: cpu@300 {
> enable-method = "psci";
> next-level-cache = <&L2_300>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> +   #cooling-cells = <2>;
> L2_300: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -101,6 +106,7 @@ CPU4: cpu@400 {
> enable-method = "psci";
> next-level-cache = <&L2_400>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> +   #cooling-cells = <2>;
> L2_400: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -114,6 +120,7 @@ CPU5: cpu@500 {
> enable-method = "psci";
> next-level-cache = <&L2_500>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> +   #cooling-cells = <2>;
> L2_500: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -128,6 +135,7 @@ CPU6: cpu@600 {
> enable-method = "psci";
> next-level-cache = <&L2_600>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> +   #cooling-cells = <2>;
> L2_600: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -141,6 +149,7 @@ CPU7: cpu@700 {
> enable-method = "psci";
> next-level-cache = <&L2_700>;
> qcom,freq-domain = <&cpufreq_hw 2>;
> +   #cooling-cells = <2>;
> L2_700: l2-cache {
>   compatible = "cache";
>   next-level-cache = <&L3_0>;
> @@ -682,6 +691,28 @@ pdc: interrupt-controller@b22 {
> interrupt-controller;
> };
>
> +   tsens0: thermal-sensor@c222000 {
> +   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> +   reg = <0 0x0C263000 0 0x1ff>, /* TM */
> + <0 0x0C222000 0 0x8>; /* SROT */
> +   #qcom,sensors = <15>;
> +   interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
> +<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
> +   interrupt-names = "uplow", "critical";
> +   #thermal-sensor-cells = <1>;
> +   };
> +
> +   tsens1: thermal-sensor@c223000 {
> +   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> +   reg = <0 0x0C265000 0 0x1ff>, /* TM */
> + <0 0x0c22300

[PATCH v1 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-19 Thread Robert Foss 
sm8350 has 29 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle their
frequencies on crossing passive temperature thresholds.

Signed-off-by: Robert Foss 
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 829 +++
 1 file changed, 829 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 4abdba78cec1..424887652f47 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <&intc>;
@@ -46,6 +47,7 @@ CPU0: cpu@0 {
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_0: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -62,6 +64,7 @@ CPU1: cpu@100 {
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_100: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -75,6 +78,7 @@ CPU2: cpu@200 {
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_200: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -88,6 +92,7 @@ CPU3: cpu@300 {
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_300: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -101,6 +106,7 @@ CPU4: cpu@400 {
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_400: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -114,6 +120,7 @@ CPU5: cpu@500 {
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_500: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -128,6 +135,7 @@ CPU6: cpu@600 {
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_600: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -141,6 +149,7 @@ CPU7: cpu@700 {
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
+   #cooling-cells = <2>;
L2_700: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -682,6 +691,28 @@ pdc: interrupt-controller@b22 {
interrupt-controller;
};
 
+   tsens0: thermal-sensor@c222000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0C263000 0 0x1ff>, /* TM */
+ <0 0x0C222000 0 0x8>; /* SROT */
+   #qcom,sensors = <15>;
+   interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "uplow", "critical";
+   #thermal-sensor-cells = <1>;
+   };
+
+   tsens1: thermal-sensor@c223000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0C265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+   #qcom,sensors = <14>;
+   interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "uplow", "c