[PATCH v1 4/4] arm: dts: mt7623: add PCIe related nodes

2017-09-19 Thread Ryder Lee 
This patch adds devices nodes and updates pinmux setting for the PICe
function block. Just note that PCIe port2 PHY is shared with U3 port.

Signed-off-by: Ryder Lee 
---
 arch/arm/boot/dts/mt7623.dtsi | 108 ++
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 +++
 2 files changed, 138 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index e11e5e7..7d78471 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -872,6 +872,114 @@
#reset-cells = <1>;
};
 
+   pcie: pcie-controller@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = < CLK_TOP_ETHIF_SEL>,
+< CLK_HIFSYS_PCIE0>,
+< CLK_HIFSYS_PCIE1>,
+< CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = < MT2701_HIFSYS_PCIE0_RST>,
+< MT2701_HIFSYS_PCIE1_RST>,
+< MT2701_HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <_port PHY_TYPE_PCIE>,
+  <_port PHY_TYPE_PCIE>,
+  < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = < MT2701_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "disabled";
+   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   device_type = "pci";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   device_type = "pci";
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   device_type = "pci";
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a149000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0 0x1a149900 0 0x0700>;
+   clocks = <>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a14a000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie1_port:

[PATCH v1 4/4] arm: dts: mt7623: add PCIe related nodes

2017-09-19 Thread Ryder Lee 
This patch adds devices nodes and updates pinmux setting for the PICe
function block. Just note that PCIe port2 PHY is shared with U3 port.

Signed-off-by: Ryder Lee 
---
 arch/arm/boot/dts/mt7623.dtsi | 108 ++
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |  30 +++
 2 files changed, 138 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index e11e5e7..7d78471 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -872,6 +872,114 @@
#reset-cells = <1>;
};
 
+   pcie: pcie-controller@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0 0x1a14 0 0x1000>, /* PCIe shared registers */
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   clocks = < CLK_TOP_ETHIF_SEL>,
+< CLK_HIFSYS_PCIE0>,
+< CLK_HIFSYS_PCIE1>,
+< CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   resets = < MT2701_HIFSYS_PCIE0_RST>,
+< MT2701_HIFSYS_PCIE1_RST>,
+< MT2701_HIFSYS_PCIE2_RST>;
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phys = <_port PHY_TYPE_PCIE>,
+  <_port PHY_TYPE_PCIE>,
+  < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = < MT2701_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "disabled";
+   ranges = <0x8100 0 0x1a16 0 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   device_type = "pci";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 193 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   device_type = "pci";
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 194 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   device_type = "pci";
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 195 
IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a149000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0 0x1a149900 0 0x0700>;
+   clocks = <>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0 0x1a14a000 0 0x0700>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   pcie1_port: pcie-phy@1a14a900 {
+