[PATCH v1 4/9] arm: dts: mt2712: Add clock controller device nodes
From: Weiyi LuAdd clock controller nodes for MT2712, include topckgen, infracfg, pericfg, mcucfg and apmixedsys. This patch also add six oscillators that provide clocks for MT2712. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 92e4c50..6338a1f 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -5,6 +5,7 @@ * SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#include #include #include #include "mt2712-pinfunc.h" @@ -74,6 +75,48 @@ #clock-cells = <0>; }; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2600>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + clkfpc: oscillator@2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000>; + clock-output-names = "clkfpc"; + }; + + clkaud_ext_i_0: oscillator@3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <650>; + clock-output-names = "clkaud_ext_i_0"; + }; + + clkaud_ext_i_1: oscillator@4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <196608000>; + clock-output-names = "clkaud_ext_i_1"; + }; + + clkaud_ext_i_2: oscillator@5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <180633600>; + clock-output-names = "clkaud_ext_i_2"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <>; @@ -87,6 +130,24 @@ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; }; + topckgen: syscon@1000 { + compatible = "mediatek,mt2712-topckgen", "syscon"; + reg = <0 0x1000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2712-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2712-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + syscfg_pctl_a: syscfg_pctl_a@10005000 { compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; @@ -114,6 +175,18 @@ status = "disabled"; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2712-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + mcucfg: syscon@1022 { + compatible = "mediatek,mt2712-mcucfg", "syscon"; + reg = <0 0x1022 0 0x1000>; + #clock-cells = <1>; + }; + sysirq: interrupt-controller@10220a80 { compatible = "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq"; @@ -185,5 +258,47 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + mfgcfg: syscon@1300 { + compatible = "mediatek,mt2712-mfgcfg", "syscon"; + reg = <0 0x1300 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@1400 { + compatible = "mediatek,mt2712-mmsys", "syscon"; + reg = <0 0x1400 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@1500 { + compatible = "mediatek,mt2712-imgsys", "syscon"; + reg = <0 0x1500 0 0x1000>; + #clock-cells = <1>; + }; + + bdpsys: syscon@1501 { + compatible = "mediatek,mt2712-bdpsys", "syscon"; + reg = <0 0x1501 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@1600 { + compatible = "mediatek,mt2712-vdecsys", "syscon"; + reg = <0 0x1600 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@1800 { + compatible = "mediatek,mt2712-vencsys", "syscon"; + reg = <0 0x1800 0 0x1000>; +
[PATCH v1 4/9] arm: dts: mt2712: Add clock controller device nodes
From: Weiyi Lu Add clock controller nodes for MT2712, include topckgen, infracfg, pericfg, mcucfg and apmixedsys. This patch also add six oscillators that provide clocks for MT2712. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 92e4c50..6338a1f 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -5,6 +5,7 @@ * SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#include #include #include #include "mt2712-pinfunc.h" @@ -74,6 +75,48 @@ #clock-cells = <0>; }; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2600>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + clkfpc: oscillator@2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000>; + clock-output-names = "clkfpc"; + }; + + clkaud_ext_i_0: oscillator@3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <650>; + clock-output-names = "clkaud_ext_i_0"; + }; + + clkaud_ext_i_1: oscillator@4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <196608000>; + clock-output-names = "clkaud_ext_i_1"; + }; + + clkaud_ext_i_2: oscillator@5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <180633600>; + clock-output-names = "clkaud_ext_i_2"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <>; @@ -87,6 +130,24 @@ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; }; + topckgen: syscon@1000 { + compatible = "mediatek,mt2712-topckgen", "syscon"; + reg = <0 0x1000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2712-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2712-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + syscfg_pctl_a: syscfg_pctl_a@10005000 { compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; @@ -114,6 +175,18 @@ status = "disabled"; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2712-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + mcucfg: syscon@1022 { + compatible = "mediatek,mt2712-mcucfg", "syscon"; + reg = <0 0x1022 0 0x1000>; + #clock-cells = <1>; + }; + sysirq: interrupt-controller@10220a80 { compatible = "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq"; @@ -185,5 +258,47 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + mfgcfg: syscon@1300 { + compatible = "mediatek,mt2712-mfgcfg", "syscon"; + reg = <0 0x1300 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@1400 { + compatible = "mediatek,mt2712-mmsys", "syscon"; + reg = <0 0x1400 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@1500 { + compatible = "mediatek,mt2712-imgsys", "syscon"; + reg = <0 0x1500 0 0x1000>; + #clock-cells = <1>; + }; + + bdpsys: syscon@1501 { + compatible = "mediatek,mt2712-bdpsys", "syscon"; + reg = <0 0x1501 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@1600 { + compatible = "mediatek,mt2712-vdecsys", "syscon"; + reg = <0 0x1600 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@1800 { + compatible = "mediatek,mt2712-vencsys", "syscon"; + reg = <0 0x1800 0 0x1000>; + #clock-cells = <1>; + }; + +