[PATCH v10 14/14] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan R
---
.../devicetree/bindings/cpufreq/krait-cpufreq.txt | 363 +
1 file changed, 363 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
new file mode 100644
index 000..7b083c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
@@ -0,0 +1,363 @@
+QCOM KRAIT CPUFreq and OPP bindings
+===
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage value of each OPP varies
+based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
+defines the voltage and current value based on the speed/pvs/version
+combination blown in the efuse. The qcom-cpufreq driver reads the efuse
+value from the SoC to provide the OPP framework with required information.
+This is used to determine the voltage and current value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'operating-points-v2-krait-cpu' for ipq8064, apq8064, msm8960,
+ msm8974.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the
+ speedbin/pvs/version that is used to select the right
+ voltage/current value pair. Note that the length field of the
+ nvmem-cell is used to differentiate between format 'A' or 'B'
+ efuse settings. len of '4' bytes is for format 'A' and '8'
+ bytes for format 'B'. Please refer the for nvmem-cells
+ bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+ and also examples below for both the cases.
+Example 1:
+-
+
+/* For arch/arm/boot/dts/apq8064.dtsi --> format 'A' */
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ cpu-idle-states = <_SPC>;
+ operating-points-v2 = <_opp_table>;
+ };
+};
+
+qfprom: qfprom@70 {
+ compatible = "qcom,qfprom";
+ reg = <0x0070 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pvs_efuse: pvs {
+ reg = <0xc0 0x4>;
+ };
+};
+
+cpu_opp_table: opp-table {
+ compatible = "operating-points-v2-krait-cpu";
+ nvmem-cells = <_efuse>;
+
+ /*
+* Missing opp-shared property means CPUs switch DVFS states
+* independently.
+*/
+
+ opp-91800 {
+ opp-hz = /bits/ 64 <91800>;
+ opp-microvolt-speed0-pvs0-v0 = <110>;
+ opp-microvolt-speed0-pvs1-v0 = <105>;
+ opp-microvolt-speed0-pvs3-v0 = <100>;
+ opp-microvolt-speed0-pvs4-v0 = <975000>;
+ opp-microvolt-speed1-pvs0-v0 = <1025000>;
+ opp-microvolt-speed1-pvs1-v0 = <100>;
+ opp-microvolt-speed1-pvs2-v0 = <95>;
+ opp-microvolt-speed1-pvs3-v0 = <925000>;
+ opp-microvolt-speed1-pvs4-v0 = <90>;
+ opp-microvolt-speed1-pvs5-v0 = <90>;
+ opp-microvolt-speed1-pvs6-v0 = <90>;
+ opp-microvolt-speed2-pvs0-v0 = <975000>;
+ opp-microvolt-speed2-pvs1-v0 = <95>;
+ opp-microvolt-speed2-pvs2-v0 = <925000>;
+ opp-microvolt-speed2-pvs3-v0 = <912500>;
+ opp-microvolt-speed2-pvs4-v0 = <90>;
+ opp-microvolt-speed2-pvs5-v0 = <90>;
+
[PATCH v10 14/14] dt-bindings: cpufreq: Document operating-points-v2-krait-cpu
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-cpufreq driver
reads the efuse value from the SoC to provide the required information
that is used to determine the voltage and current value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
Reviewed-by: Rob Herring
Acked-by: Viresh Kumar
Signed-off-by: Sricharan R
---
.../devicetree/bindings/cpufreq/krait-cpufreq.txt | 363 +
1 file changed, 363 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
new file mode 100644
index 000..7b083c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/krait-cpufreq.txt
@@ -0,0 +1,363 @@
+QCOM KRAIT CPUFreq and OPP bindings
+===
+
+In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
+that has KRAIT processors the voltage value of each OPP varies
+based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
+defines the voltage and current value based on the speed/pvs/version
+combination blown in the efuse. The qcom-cpufreq driver reads the efuse
+value from the SoC to provide the OPP framework with required information.
+This is used to determine the voltage and current value for each OPP of
+operating-points-v2 table when it is parsed by the OPP framework.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'operating-points-v2-krait-cpu' for ipq8064, apq8064, msm8960,
+ msm8974.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the
+ speedbin/pvs/version that is used to select the right
+ voltage/current value pair. Note that the length field of the
+ nvmem-cell is used to differentiate between format 'A' or 'B'
+ efuse settings. len of '4' bytes is for format 'A' and '8'
+ bytes for format 'B'. Please refer the for nvmem-cells
+ bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+ and also examples below for both the cases.
+Example 1:
+-
+
+/* For arch/arm/boot/dts/apq8064.dtsi --> format 'A' */
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ cpu-idle-states = <_SPC>;
+ operating-points-v2 = <_opp_table>;
+ };
+};
+
+qfprom: qfprom@70 {
+ compatible = "qcom,qfprom";
+ reg = <0x0070 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ pvs_efuse: pvs {
+ reg = <0xc0 0x4>;
+ };
+};
+
+cpu_opp_table: opp-table {
+ compatible = "operating-points-v2-krait-cpu";
+ nvmem-cells = <_efuse>;
+
+ /*
+* Missing opp-shared property means CPUs switch DVFS states
+* independently.
+*/
+
+ opp-91800 {
+ opp-hz = /bits/ 64 <91800>;
+ opp-microvolt-speed0-pvs0-v0 = <110>;
+ opp-microvolt-speed0-pvs1-v0 = <105>;
+ opp-microvolt-speed0-pvs3-v0 = <100>;
+ opp-microvolt-speed0-pvs4-v0 = <975000>;
+ opp-microvolt-speed1-pvs0-v0 = <1025000>;
+ opp-microvolt-speed1-pvs1-v0 = <100>;
+ opp-microvolt-speed1-pvs2-v0 = <95>;
+ opp-microvolt-speed1-pvs3-v0 = <925000>;
+ opp-microvolt-speed1-pvs4-v0 = <90>;
+ opp-microvolt-speed1-pvs5-v0 = <90>;
+ opp-microvolt-speed1-pvs6-v0 = <90>;
+ opp-microvolt-speed2-pvs0-v0 = <975000>;
+ opp-microvolt-speed2-pvs1-v0 = <95>;
+ opp-microvolt-speed2-pvs2-v0 = <925000>;
+ opp-microvolt-speed2-pvs3-v0 = <912500>;
+ opp-microvolt-speed2-pvs4-v0 = <90>;
+ opp-microvolt-speed2-pvs5-v0 = <90>;
+
