[PATCH v10 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding

[Purna Chandra Mandal]

- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc

Signed-off-by: Purna Chandra Mandal 

Note: Please pull this complete series through the MIPS tree.

---

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Changes in v6: None
Changes in v3: None
Changes in v2: None

---
 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236 
 arch/mips/boot/dts/pic32/pic32mzda.dtsi |  63 +---
 arch/mips/boot/dts/pic32/pic32mzda_sk.dts   |   5 +-
 3 files changed, 45 insertions(+), 259 deletions(-)
 delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi

diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi 
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal 
- * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
-   POSC:posc_clk { /* On-chip primary oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   };
-
-   FRC:frc_clk { /* internal FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <800>;
-   };
-
-   BFRC:bfrc_clk { /* internal backup FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <800>;
-   };
-
-   LPRC:lprc_clk { /* internal low-power FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32000>;
-   };
-
-   /* UPLL provides clock to USBCORE */
-   UPLL:usb_phy_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   clock-output-names = "usbphy_clk";
-   };
-
-   TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <400>;
-   status = "disabled";
-   };
-
-   /* external clock input on REFCLKIx pin */
-   REFIx:refix_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   status = "disabled";
-   };
-
-   /* PIC32 specific clks */
-   pic32_clktree {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   reg = <0x1f801200 0x200>;
-   compatible = "microchip,pic32mzda-clk";
-   ranges = <0 0x1f801200 0x200>;
-
-   /* secondary oscillator; external input on SOSCI pin */
-   SOSC:sosc_clk@0 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-sosc";
-   clock-frequency = <32768>;
-   reg = <0x000 0x10>,   /* enable reg */
- <0x1d0 0x10>; /* status reg */
-   microchip,bit-mask = <0x02>; /* enable mask */
-   microchip,status-bit-mask = <0x10>; /* status-mask*/
-   };
-
-   FRCDIV:frcdiv_clk {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-frcdivclk";
-   clocks = <>;
-   clock-output-names = "frcdiv_clk";
-   };
-
-   /* System PLL clock */
-   SYSPLL:spll_clk@020 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-syspll";
-   reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
-   clocks = <>, <>;
-   clock-output-names = "sys_pll";
-   microchip,status-bit-mask = <0x80>; /* SPLLRDY */
-   };
-
-   /* system clock; mux with postdiv & slew */
-   SYSCLK:sys_clk@1c0 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-sysclk-v2";
-   reg = <0x1c0 0x04>; /* SLEWCON */
-   clocks = <>, <>, <>, <>,
-<>, <>;
-   microchip,clock-indices = <0>, <1>, <2>, <4>,
- 

[PATCH v10 3/3] MIPS: dts: pic32: Update dts to reflect new PIC32MZDA clk binding

[Purna Chandra Mandal]

- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc

Signed-off-by: Purna Chandra Mandal 

Note: Please pull this complete series through the MIPS tree.

---

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- now clock nodes definition is merged with core .dtsi file
- only one rootclk is now part of DT
- clock clients also updated based on new binding doc
Changes in v6: None
Changes in v3: None
Changes in v2: None

---
 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi | 236 
 arch/mips/boot/dts/pic32/pic32mzda.dtsi |  63 +---
 arch/mips/boot/dts/pic32/pic32mzda_sk.dts   |   5 +-
 3 files changed, 45 insertions(+), 259 deletions(-)
 delete mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi

diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi 
b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
deleted file mode 100644
index ef13350..000
--- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Device Tree Source for PIC32MZDA clock data
- *
- * Purna Chandra Mandal 
- * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
- *
- * Licensed under GPLv2 or later.
- */
-
-/* all fixed rate clocks */
-
-/ {
-   POSC:posc_clk { /* On-chip primary oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   };
-
-   FRC:frc_clk { /* internal FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <800>;
-   };
-
-   BFRC:bfrc_clk { /* internal backup FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <800>;
-   };
-
-   LPRC:lprc_clk { /* internal low-power FRC oscillator */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <32000>;
-   };
-
-   /* UPLL provides clock to USBCORE */
-   UPLL:usb_phy_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   clock-output-names = "usbphy_clk";
-   };
-
-   TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <400>;
-   status = "disabled";
-   };
-
-   /* external clock input on REFCLKIx pin */
-   REFIx:refix_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <2400>;
-   status = "disabled";
-   };
-
-   /* PIC32 specific clks */
-   pic32_clktree {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   reg = <0x1f801200 0x200>;
-   compatible = "microchip,pic32mzda-clk";
-   ranges = <0 0x1f801200 0x200>;
-
-   /* secondary oscillator; external input on SOSCI pin */
-   SOSC:sosc_clk@0 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-sosc";
-   clock-frequency = <32768>;
-   reg = <0x000 0x10>,   /* enable reg */
- <0x1d0 0x10>; /* status reg */
-   microchip,bit-mask = <0x02>; /* enable mask */
-   microchip,status-bit-mask = <0x10>; /* status-mask*/
-   };
-
-   FRCDIV:frcdiv_clk {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-frcdivclk";
-   clocks = <>;
-   clock-output-names = "frcdiv_clk";
-   };
-
-   /* System PLL clock */
-   SYSPLL:spll_clk@020 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-syspll";
-   reg = <0x020 0x10>, /* SPLL register */
- <0x1d0 0x10>; /* CLKSTAT register */
-   clocks = <>, <>;
-   clock-output-names = "sys_pll";
-   microchip,status-bit-mask = <0x80>; /* SPLLRDY */
-   };
-
-   /* system clock; mux with postdiv & slew */
-   SYSCLK:sys_clk@1c0 {
-   #clock-cells = <0>;
-   compatible = "microchip,pic32mzda-sysclk-v2";
-   reg = <0x1c0 0x04>; /* SLEWCON */
-   clocks = <>, <>, <>, <>,
-<>, <>;
-   microchip,clock-indices = <0>, <1>, <2>, <4>,
- <5>,