Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC

2020-07-15 Thread Vinod Koul 
Hi Alim,

On 16-07-20, 06:47, Alim Akhtar wrote:

> > > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > > +*phy) {
> > > + int ret = 0;
> > 
> > superfluous init, am sure I flagged it before as well
> > 
> Yes, you did, but 0-DAY CI kernel test gave warning [1], so I kept this as
> it is.
> [1] https://lkml.org/lkml/2020/7/3/81

But you moved away from return below to goto, so that is no longer
the case. First use of ret is for clk_prepare_enable() call below which
is not conditional hence this is superfluous. Earlier it was not as it was
conditional so required to be initialized

> 
> > > +
> > > + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > > + if (IS_ERR(phy->tx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > > + if (IS_ERR(phy->rx0_symbol_clk)) {
> > > + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > > + goto out;
> > > + }
> > > +
> > > + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > > + if (ret) {
> > > + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> > __func__, ret);
> > > + goto out;
> > > + }
-- 
~Vinod

RE: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC

2020-07-15 Thread Alim Akhtar 
Hi Vinod,

> -Original Message-
> From: Vinod Koul 
> Sent: 13 July 2020 11:48
> To: Alim Akhtar 
> Cc: robh...@kernel.org; k...@kernel.org; kwmad@samsung.com;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-samsung-...@vger.kernel.org; kis...@ti.com
> Subject: Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for
samsung
> SoC
> 
> On 03-07-20, 22:41, Alim Akhtar wrote:
> 
> > +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> > +   END_UFS_PHY_CFG
> > +};
> 
> This is dummy, why not add a check to make config optional?
> 
Currently this is dummy, however this might be used for the similar platform
which do some phy tunning post init.
Will just remove this for now for this platform, will add this check in
driver.

> > +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy
> > +*phy) {
> > +   int ret = 0;
> 
> superfluous init, am sure I flagged it before as well
> 
Yes, you did, but 0-DAY CI kernel test gave warning [1], so I kept this as
it is.
[1] https://lkml.org/lkml/2020/7/3/81

> > +
> > +   phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> > +   if (IS_ERR(phy->tx0_symbol_clk)) {
> > +   dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> > +   goto out;
> > +   }
> > +
> > +   phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> > +   if (IS_ERR(phy->rx0_symbol_clk)) {
> > +   dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> > +   goto out;
> > +   }
> > +
> > +   phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> > +   if (IS_ERR(phy->rx0_symbol_clk)) {
> > +   dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> > +   goto out;
> > +   }
> > +
> > +   ret = clk_prepare_enable(phy->tx0_symbol_clk);
> > +   if (ret) {
> > +   dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > +   goto out;
> > +   }
> > +
> > +   ret = clk_prepare_enable(phy->rx0_symbol_clk);
> > +   if (ret) {
> > +   dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n",
> __func__, ret);
> > +   clk_disable_unprepare(phy->tx0_symbol_clk);
> > +   goto out;
> > +   }
> > +
> > +   ret = clk_prepare_enable(phy->rx1_symbol_clk);
> > +   if (ret) {
> > +   dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n",
> __func__, ret);
> > +   clk_disable_unprepare(phy->tx0_symbol_clk);
> > +   clk_disable_unprepare(phy->rx0_symbol_clk);
> 
> maybe it will look better if we add common rollback and jump to proper
labels
> 
Sure, will change in next version.

> > +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) {
> > +   int ret;
> > +
> > +   phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> > +   if (IS_ERR(phy->ref_clk))
> > +   dev_err(phy->dev, "failed to get ref_clk clock\n");
> > +
> > +   ret = clk_prepare_enable(phy->ref_clk);
> > +   if (ret) {
> > +   dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
__func__,
> ret);
> > +   return ret;
> > +   }
> > +
> > +   dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n",
> > +clk_get_rate(phy->ref_clk));
> 
> debug pls
> 
Sure, will change

> > +static int samsung_ufs_phy_init(struct phy *phy) {
> > +   struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);
> 
> ss_phy perhaps?
> 
Sure, will change 

> > +   int ret;
> > +
> > +   _phy->lane_cnt = phy->attrs.bus_width;
> > +   _phy->ufs_phy_state = CFG_PRE_INIT;
> > +
> > +   if (_phy->drvdata->has_symbol_clk) {
> > +   ret = samsung_ufs_phy_symbol_clk_init(_phy);
> > +   if (ret)
> > +   dev_err(_phy->dev, "failed to set ufs phy symbol
> clocks\n");
> > +   }
> > +
> > +   ret = samsung_ufs_phy_clks_init(_phy);
> > +   if (ret)
> > +   dev_err(_phy->dev, "failed to set ufs phy  clocks\n");
> > +
> > +   samsung_ufs_phy_calibrate(phy);
> > +
> > +   return 0;
> 
> not return samsung_ufs_phy_calibrate() ?
> --
Will add an error path.

> ~Vinod

Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC

2020-07-13 Thread Vinod Koul 
On 03-07-20, 22:41, Alim Akhtar wrote:

> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> + END_UFS_PHY_CFG
> +};

This is dummy, why not add a check to make config optional?

> +static int samsung_ufs_phy_symbol_clk_init(struct samsung_ufs_phy *phy)
> +{
> + int ret = 0;

superfluous init, am sure I flagged it before as well

> +
> + phy->tx0_symbol_clk = devm_clk_get(phy->dev, "tx0_symbol_clk");
> + if (IS_ERR(phy->tx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get tx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx0_symbol_clk = devm_clk_get(phy->dev, "rx0_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx0_symbol_clk clock\n");
> + goto out;
> + }
> +
> + phy->rx1_symbol_clk = devm_clk_get(phy->dev, "rx1_symbol_clk");
> + if (IS_ERR(phy->rx0_symbol_clk)) {
> + dev_err(phy->dev, "failed to get rx1_symbol_clk clock\n");
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->tx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: tx0_symbol_clk enable failed %d\n", 
> __func__, ret);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx0_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx0_symbol_clk enable failed %d\n", 
> __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + goto out;
> + }
> +
> + ret = clk_prepare_enable(phy->rx1_symbol_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: rx1_symbol_clk enable failed %d\n", 
> __func__, ret);
> + clk_disable_unprepare(phy->tx0_symbol_clk);
> + clk_disable_unprepare(phy->rx0_symbol_clk);

maybe it will look better if we add common rollback and jump to proper
labels

> +static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy)
> +{
> + int ret;
> +
> + phy->ref_clk = devm_clk_get(phy->dev, "ref_clk");
> + if (IS_ERR(phy->ref_clk))
> + dev_err(phy->dev, "failed to get ref_clk clock\n");
> +
> + ret = clk_prepare_enable(phy->ref_clk);
> + if (ret) {
> + dev_err(phy->dev, "%s: ref_clk enable failed %d\n", __func__, 
> ret);
> + return ret;
> + }
> +
> + dev_info(phy->dev, "UFS MPHY ref_clk_rate = %ld\n", 
> clk_get_rate(phy->ref_clk));

debug pls

> +static int samsung_ufs_phy_init(struct phy *phy)
> +{
> + struct samsung_ufs_phy *_phy = get_samsung_ufs_phy(phy);

ss_phy perhaps?

> + int ret;
> +
> + _phy->lane_cnt = phy->attrs.bus_width;
> + _phy->ufs_phy_state = CFG_PRE_INIT;
> +
> + if (_phy->drvdata->has_symbol_clk) {
> + ret = samsung_ufs_phy_symbol_clk_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy symbol 
> clocks\n");
> + }
> +
> + ret = samsung_ufs_phy_clks_init(_phy);
> + if (ret)
> + dev_err(_phy->dev, "failed to set ufs phy  clocks\n");
> +
> + samsung_ufs_phy_calibrate(phy);
> +
> + return 0;

not return samsung_ufs_phy_calibrate() ?
-- 
~Vinod

Re: [PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC

2020-07-11 Thread Alim Akhtar 
Hi Vinod
Gentle Reminder !!

On Fri, Jul 3, 2020 at 11:02 PM Alim Akhtar  wrote:
>
> This patch introduces Samsung UFS PHY driver. This driver
> supports to deal with phy calibration and power control
> according to UFS host driver's behavior.
>
> [Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
> Reported-by: kernel test robot 
> Reviewed-by: Kiwoong Kim 
> Signed-off-by: Seungwon Jeon 
> Signed-off-by: Alim Akhtar 
> Cc: Kishon Vijay Abraham I 
> Cc: Vinod Koul 
> Tested-by: Paweł Chmiel 
> ---
>  - Changes V11 -> V12
>  * Fixed kernel test robot warnings
>
>  - Changes V10 -> V11
>  * Addressed review comments from Vinod
>
>  drivers/phy/samsung/Kconfig   |   9 +
>  drivers/phy/samsung/Makefile  |   1 +
>  drivers/phy/samsung/phy-exynos7-ufs.h |  86 ++
>  drivers/phy/samsung/phy-samsung-ufs.c | 359 ++
>  drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
>  5 files changed, 594 insertions(+)
>  create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
>  create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
>  create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index 19f2e3119343..e20d2fcc9fe7 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
>   Enable PCIe PHY support for Exynos SoC series.
>   This driver provides PHY interface for Exynos PCIe controller.
>
> +config PHY_SAMSUNG_UFS
> +   tristate "SAMSUNG SoC series UFS PHY driver"
> +   depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
> +   select GENERIC_PHY
> +   help
> + Enable this to support the Samsung UFS PHY driver for
> + Samsung SoCs. This driver provides the interface for UFS
> + host controller to do PHY related programming.
> +
>  config PHY_SAMSUNG_USB2
> tristate "Samsung USB 2.0 PHY driver"
> depends on HAS_IOMEM
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index db9b1aa0de6e..3959100fe8a2 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -2,6 +2,7 @@
>  obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)  += phy-exynos-dp-video.o
>  obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
>  obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
> +obj-$(CONFIG_PHY_SAMSUNG_UFS)  += phy-samsung-ufs.o
>  obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
>  phy-exynos-usb2-y  += phy-samsung-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)  += phy-exynos4210-usb2.o
> diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h 
> b/drivers/phy/samsung/phy-exynos7-ufs.h
> new file mode 100644
> index ..c4aab792d30e
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynos7-ufs.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UFS PHY driver data for Samsung EXYNOS7 SoC
> + *
> + * Copyright (C) 2020 Samsung Electronics Co., Ltd.
> + */
> +#ifndef _PHY_EXYNOS7_UFS_H_
> +#define _PHY_EXYNOS7_UFS_H_
> +
> +#include "phy-samsung-ufs.h"
> +
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK   0x1
> +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
> +
> +/* Calibration for phy initialization */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
> +   PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
> +   PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
> +   PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
> +   PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
> +   PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
> +   END_UFS_PHY_CFG
> +};
> +
> +static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
> +   END_UFS_PHY_CFG
> +};
> +
> +/* Calibration for HS mode series A/B */
> +static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
> +   PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
> +   PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
> +   PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
> +   /* Setting order: 1st(0x16, 2nd(0x15) */
> +   PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
> +   PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
> +   PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
> +   PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
> +   PHY_TRSV_REG_CFG(0x037, 0x43,

[PATCH v12 2/2] phy: samsung-ufs: add UFS PHY driver for samsung SoC

2020-07-03 Thread Alim Akhtar 
This patch introduces Samsung UFS PHY driver. This driver
supports to deal with phy calibration and power control
according to UFS host driver's behavior.

[Robot: -Wmissing-prototypes and -Wsometimes-uninitialized]
Reported-by: kernel test robot 
Reviewed-by: Kiwoong Kim 
Signed-off-by: Seungwon Jeon 
Signed-off-by: Alim Akhtar 
Cc: Kishon Vijay Abraham I 
Cc: Vinod Koul 
Tested-by: Paweł Chmiel 
---
 - Changes V11 -> V12
 * Fixed kernel test robot warnings

 - Changes V10 -> V11
 * Addressed review comments from Vinod

 drivers/phy/samsung/Kconfig   |   9 +
 drivers/phy/samsung/Makefile  |   1 +
 drivers/phy/samsung/phy-exynos7-ufs.h |  86 ++
 drivers/phy/samsung/phy-samsung-ufs.c | 359 ++
 drivers/phy/samsung/phy-samsung-ufs.h | 139 ++
 5 files changed, 594 insertions(+)
 create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h
 create mode 100644 drivers/phy/samsung/phy-samsung-ufs.c
 create mode 100644 drivers/phy/samsung/phy-samsung-ufs.h

diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
index 19f2e3119343..e20d2fcc9fe7 100644
--- a/drivers/phy/samsung/Kconfig
+++ b/drivers/phy/samsung/Kconfig
@@ -29,6 +29,15 @@ config PHY_EXYNOS_PCIE
  Enable PCIe PHY support for Exynos SoC series.
  This driver provides PHY interface for Exynos PCIe controller.
 
+config PHY_SAMSUNG_UFS
+   tristate "SAMSUNG SoC series UFS PHY driver"
+   depends on OF && (ARCH_EXYNOS || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the Samsung UFS PHY driver for
+ Samsung SoCs. This driver provides the interface for UFS
+ host controller to do PHY related programming.
+
 config PHY_SAMSUNG_USB2
tristate "Samsung USB 2.0 PHY driver"
depends on HAS_IOMEM
diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index db9b1aa0de6e..3959100fe8a2 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO)  += phy-exynos-dp-video.o
 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
+obj-$(CONFIG_PHY_SAMSUNG_UFS)  += phy-samsung-ufs.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
 phy-exynos-usb2-y  += phy-samsung-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)  += phy-exynos4210-usb2.o
diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h 
b/drivers/phy/samsung/phy-exynos7-ufs.h
new file mode 100644
index ..c4aab792d30e
--- /dev/null
+++ b/drivers/phy/samsung/phy-exynos7-ufs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS PHY driver data for Samsung EXYNOS7 SoC
+ *
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ */
+#ifndef _PHY_EXYNOS7_UFS_H_
+#define _PHY_EXYNOS7_UFS_H_
+
+#include "phy-samsung-ufs.h"
+
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL0x720
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK   0x1
+#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
+   PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
+   PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
+   PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
+   PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
+   PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
+   END_UFS_PHY_CFG
+};
+
+static const struct samsung_ufs_phy_cfg exynos7_post_init_cfg[] = {
+   END_UFS_PHY_CFG
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
+   PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
+   PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
+   PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
+   /* Setting order: 1st(0x16, 2nd(0x15) */
+   PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
+   PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
+   PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
+   PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
+   PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
+   PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
+   PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
+   PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
+   PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
+   PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
+