Re: [PATCH v12 2/6] doc: dt: document altera-passive-serial binding

[Alan Tull]

On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton  wrote:
> Describe an altera-passive-serial devicetree entry, required features
>
> Signed-off-by: Joshua Clayton 
> Acked-by: Rob Herring 

Signed-off-by: Alan Tull 

> ---
>  .../bindings/fpga/altera-passive-serial.txt| 29 
> ++
>  1 file changed, 29 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt 
> b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> new file mode 100644
> index ..48478bc07e29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> @@ -0,0 +1,29 @@
> +Altera Passive Serial SPI FPGA Manager
> +
> +Altera FPGAs support a method of loading the bitstream over what is
> +referred to as "passive serial".
> +The passive serial link is not technically SPI, and might require extra
> +circuits in order to play nicely with other SPI slaves on the same bus.
> +
> +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
> +
> +Required properties:
> +- compatible: Must be one of the following:
> +   "altr,fpga-passive-serial",
> +   "altr,fpga-arria10-passive-serial"
> +- reg: SPI chip select of the FPGA
> +- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
> +- nstat-gpios: status pin (referred to as nSTATUS in the manual)
> +
> +Optional properties:
> +- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
> +
> +Example:
> +   fpga: fpga@0 {
> +   compatible = "altr,fpga-passive-serial";
> +   spi-max-frequency = <2000>;
> +   reg = <0>;
> +   nconfig-gpios = < 9 GPIO_ACTIVE_LOW>;
> +   nstat-gpios = < 11 GPIO_ACTIVE_LOW>;
> +   confd-gpios = < 12 GPIO_ACTIVE_LOW>;
> +   };
> --
> 2.11.0
>

Re: [PATCH v12 2/6] doc: dt: document altera-passive-serial binding

[Alan Tull]

On Fri, Jun 2, 2017 at 3:30 PM, Joshua Clayton  wrote:
> Describe an altera-passive-serial devicetree entry, required features
>
> Signed-off-by: Joshua Clayton 
> Acked-by: Rob Herring 

Signed-off-by: Alan Tull 

> ---
>  .../bindings/fpga/altera-passive-serial.txt| 29 
> ++
>  1 file changed, 29 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt 
> b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> new file mode 100644
> index ..48478bc07e29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
> @@ -0,0 +1,29 @@
> +Altera Passive Serial SPI FPGA Manager
> +
> +Altera FPGAs support a method of loading the bitstream over what is
> +referred to as "passive serial".
> +The passive serial link is not technically SPI, and might require extra
> +circuits in order to play nicely with other SPI slaves on the same bus.
> +
> +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
> +
> +Required properties:
> +- compatible: Must be one of the following:
> +   "altr,fpga-passive-serial",
> +   "altr,fpga-arria10-passive-serial"
> +- reg: SPI chip select of the FPGA
> +- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
> +- nstat-gpios: status pin (referred to as nSTATUS in the manual)
> +
> +Optional properties:
> +- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
> +
> +Example:
> +   fpga: fpga@0 {
> +   compatible = "altr,fpga-passive-serial";
> +   spi-max-frequency = <2000>;
> +   reg = <0>;
> +   nconfig-gpios = < 9 GPIO_ACTIVE_LOW>;
> +   nstat-gpios = < 11 GPIO_ACTIVE_LOW>;
> +   confd-gpios = < 12 GPIO_ACTIVE_LOW>;
> +   };
> --
> 2.11.0
>

[PATCH v12 2/6] doc: dt: document altera-passive-serial binding

[Joshua Clayton]

Describe an altera-passive-serial devicetree entry, required features

Signed-off-by: Joshua Clayton 
Acked-by: Rob Herring 
---
 .../bindings/fpga/altera-passive-serial.txt| 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt 
b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
new file mode 100644
index ..48478bc07e29
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+   "altr,fpga-passive-serial",
+   "altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+   fpga: fpga@0 {
+   compatible = "altr,fpga-passive-serial";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   nconfig-gpios = < 9 GPIO_ACTIVE_LOW>;
+   nstat-gpios = < 11 GPIO_ACTIVE_LOW>;
+   confd-gpios = < 12 GPIO_ACTIVE_LOW>;
+   };
-- 
2.11.0

[PATCH v12 2/6] doc: dt: document altera-passive-serial binding

[Joshua Clayton]

Describe an altera-passive-serial devicetree entry, required features

Signed-off-by: Joshua Clayton 
Acked-by: Rob Herring 
---
 .../bindings/fpga/altera-passive-serial.txt| 29 ++
 1 file changed, 29 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt 
b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
new file mode 100644
index ..48478bc07e29
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+   "altr,fpga-passive-serial",
+   "altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+   fpga: fpga@0 {
+   compatible = "altr,fpga-passive-serial";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   nconfig-gpios = < 9 GPIO_ACTIVE_LOW>;
+   nstat-gpios = < 11 GPIO_ACTIVE_LOW>;
+   confd-gpios = < 12 GPIO_ACTIVE_LOW>;
+   };
-- 
2.11.0