Re: [PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
Stephen Boyd writes:
> On 08/04, Robert Jarzmik wrote:
>> Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names
>> were inadequately inverted. As a consequence, all clock operations were
>> happening on CKENB, because almost all but 2 clocks are on CKENA.
>>
>> As the clocks were activated by the bootloader in the former tests, it
>> escaped the testing that the wrong clock gate was manipulated. The error
>> was revealed by changing the pxa3xx-and driver to a module, where tupon
>> unloading the wrong clock was disabled in CKENB.
>>
>> Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
>> Signed-off-by: Robert Jarzmik
>> ---
>
> Applied to clk-fixes. Sorry, got busy last few days.
Thanks Stephen !
Cheers.
--
Robert
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Re: [PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
Stephen Boyd sb...@codeaurora.org writes: On 08/04, Robert Jarzmik wrote: Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names were inadequately inverted. As a consequence, all clock operations were happening on CKENB, because almost all but 2 clocks are on CKENA. As the clocks were activated by the bootloader in the former tests, it escaped the testing that the wrong clock gate was manipulated. The error was revealed by changing the pxa3xx-and driver to a module, where tupon unloading the wrong clock was disabled in CKENB. Fixes: 9bbb8a338fb2 (clk: pxa: add pxa3xx clock driver) Signed-off-by: Robert Jarzmik robert.jarz...@free.fr --- Applied to clk-fixes. Sorry, got busy last few days. Thanks Stephen ! Cheers. -- Robert -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
On 08/04, Robert Jarzmik wrote:
> Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names
> were inadequately inverted. As a consequence, all clock operations were
> happening on CKENB, because almost all but 2 clocks are on CKENA.
>
> As the clocks were activated by the bootloader in the former tests, it
> escaped the testing that the wrong clock gate was manipulated. The error
> was revealed by changing the pxa3xx-and driver to a module, where tupon
> unloading the wrong clock was disabled in CKENB.
>
> Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
> Signed-off-by: Robert Jarzmik
> ---
Applied to clk-fixes. Sorry, got busy last few days.
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a Linux Foundation Collaborative Project
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Re: [PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
On 08/04, Robert Jarzmik wrote: Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names were inadequately inverted. As a consequence, all clock operations were happening on CKENB, because almost all but 2 clocks are on CKENA. As the clocks were activated by the bootloader in the former tests, it escaped the testing that the wrong clock gate was manipulated. The error was revealed by changing the pxa3xx-and driver to a module, where tupon unloading the wrong clock was disabled in CKENB. Fixes: 9bbb8a338fb2 (clk: pxa: add pxa3xx clock driver) Signed-off-by: Robert Jarzmik robert.jarz...@free.fr --- Applied to clk-fixes. Sorry, got busy last few days. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names
were inadequately inverted. As a consequence, all clock operations were
happening on CKENB, because almost all but 2 clocks are on CKENA.
As the clocks were activated by the bootloader in the former tests, it
escaped the testing that the wrong clock gate was manipulated. The error
was revealed by changing the pxa3xx-and driver to a module, where tupon
unloading the wrong clock was disabled in CKENB.
Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
Signed-off-by: Robert Jarzmik
---
Since v1: added Fixes:
---
drivers/clk/pxa/clk-pxa3xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index c677b9ab5367..4af4eed5f89f 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -126,7 +126,7 @@ PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
-#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? : )
+#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? : )
#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
div_hp, bit, is_lp, flags) \
PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
--
2.1.4
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[PATCH v2] clk: pxa: pxa3xx: fix CKEN register access
Clocks 0 to 31 are on CKENA, and not CKENB. The clock register names
were inadequately inverted. As a consequence, all clock operations were
happening on CKENB, because almost all but 2 clocks are on CKENA.
As the clocks were activated by the bootloader in the former tests, it
escaped the testing that the wrong clock gate was manipulated. The error
was revealed by changing the pxa3xx-and driver to a module, where tupon
unloading the wrong clock was disabled in CKENB.
Fixes: 9bbb8a338fb2 (clk: pxa: add pxa3xx clock driver)
Signed-off-by: Robert Jarzmik robert.jarz...@free.fr
---
Since v1: added Fixes:
---
drivers/clk/pxa/clk-pxa3xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
index c677b9ab5367..4af4eed5f89f 100644
--- a/drivers/clk/pxa/clk-pxa3xx.c
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -126,7 +126,7 @@ PARENTS(pxa3xx_ac97_bus) = { ring_osc_60mhz, ac97 };
PARENTS(pxa3xx_sbus) = { ring_osc_60mhz, system_bus };
PARENTS(pxa3xx_smemcbus) = { ring_osc_60mhz, smemc };
-#define CKEN_AB(bit) ((CKEN_ ## bit 31) ? CKENA : CKENB)
+#define CKEN_AB(bit) ((CKEN_ ## bit 31) ? CKENB : CKENA)
#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
div_hp, bit, is_lp, flags) \
PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
--
2.1.4
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