Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
On Mon, Mar 04, 2019 at 05:29:22PM +, Suzuki K Poulose wrote: [...] > > > To support for a funnel without any register address range (we have > > > support replicator like this mode), we also need to extend the driver > > > drivers/hwtracing/coresight/coresight-funnel.c. > > > > > > Mathieu, Mike, Suzuki, could you help confirm this is the right > > > direction we should move forward to? > > > > Leo, thanks for testing this out. Shiwanglai, please add Suzuki and > > myself to future revision of this set - this will help you getting a > > timely response for your work. Yeah, I didn't give a good example for this; just remind to Wanglai, usually we can add maintainers' email address in the "To:" list so this will be more friendly for email filters. > > As Leo pointed out we already have support for replicators that don't > > have a register map and the same thing should be done in this case. > > But contrary to what was done for replicators, I think we should keep > > the drivers in the same file as Russell did here[1]. That way we can > > keep all things funnel at the same place and reduce the amount of > > kernel configuration options. > > I back that. I have already merged the static and programmable replicators > into one and this should be out here soon. So, I back the single driver > approach for funnels. That's great! Thanks for advices, Mathieu & Suzuki. Will sync with you offline for proceeding. Thanks, Leo Yan
Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
Hi,
On 04/03/2019 17:18, Mathieu Poirier wrote:
On Sat, 2 Mar 2019 at 06:00, Leo Yan wrote:
On Sat, Mar 02, 2019 at 09:45:22AM +, Shiwanglai wrote:
[...]
+ /* Top internals */
+ funnel@ec031000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xec031000 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ top_funnel_out: endpoint {
+ remote-endpoint =
+ <_etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ top_funnel_in0: endpoint {
+ remote-endpoint =
+ <_etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
Here should s/<0>/<1>; otherwise DTC will complain warning for mismatching between
'port@1' and 'reg = <0>'.
-- if reg set to 1, then there's no data output from cluster 1 to top.
Thanks for the info, Wanglai. Now I see why write as it is.
I can confirm if directly use your patch with perf with mainline
kernel I can capture CoreSight trace data successfully on Hikey960
board.
But since this DT binding will introduce DTC warning, I personally
think we can improve for this with below method:
We can create a funnel node named "funnel_combo", and we don't need to
specify register address range for it; and cluster 0 and cluster 1 will
output to "funnel_combo" and "funnel_combo" will output to the top
funnel. Thus the DT binding will write as below.
To support for a funnel without any register address range (we have
support replicator like this mode), we also need to extend the driver
drivers/hwtracing/coresight/coresight-funnel.c.
Mathieu, Mike, Suzuki, could you help confirm this is the right
direction we should move forward to?
Leo, thanks for testing this out. Shiwanglai, please add Suzuki and
myself to future revision of this set - this will help you getting a
timely response for your work.
As Leo pointed out we already have support for replicators that don't
have a register map and the same thing should be done in this case.
But contrary to what was done for replicators, I think we should keep
the drivers in the same file as Russell did here[1]. That way we can
keep all things funnel at the same place and reduce the amount of
kernel configuration options.
I back that. I have already merged the static and programmable replicators
into one and this should be out here soon. So, I back the single driver
approach for funnels.
Cheers
Suzuki
Regards,
Mathieu
[1].
https://elixir.bootlin.com/linux/latest/source/drivers/tty/serial/amba-pl011.c#L2819
Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
On Sat, 2 Mar 2019 at 06:00, Leo Yan wrote:
>
> On Sat, Mar 02, 2019 at 09:45:22AM +, Shiwanglai wrote:
>
> [...]
>
> > > + /* Top internals */
> > > + funnel@ec031000 {
> > > + compatible = "arm,coresight-funnel", "arm,primecell";
> > > + reg = <0 0xec031000 0 0x1000>;
> > > + clocks = <_ctrl HI3660_PCLK>;
> > > + clock-names = "apb_pclk";
> > > +
> > > + out-ports {
> > > + port {
> > > + top_funnel_out: endpoint {
> > > + remote-endpoint =
> > > + <_etf_in>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + in-ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port@0 {
> > > + reg = <0>;
> > > + top_funnel_in0: endpoint {
> > > + remote-endpoint =
> > > + <_etf_out>;
> > > + };
> > > + };
> > > +
> > > + port@1 {
> > > + reg = <0>;
> >
> > Here should s/<0>/<1>; otherwise DTC will complain warning for mismatching
> > between 'port@1' and 'reg = <0>'.
>
> > -- if reg set to 1, then there's no data output from cluster 1 to top.
>
> Thanks for the info, Wanglai. Now I see why write as it is.
>
> I can confirm if directly use your patch with perf with mainline
> kernel I can capture CoreSight trace data successfully on Hikey960
> board.
>
> But since this DT binding will introduce DTC warning, I personally
> think we can improve for this with below method:
>
> We can create a funnel node named "funnel_combo", and we don't need to
> specify register address range for it; and cluster 0 and cluster 1 will
> output to "funnel_combo" and "funnel_combo" will output to the top
> funnel. Thus the DT binding will write as below.
>
> To support for a funnel without any register address range (we have
> support replicator like this mode), we also need to extend the driver
> drivers/hwtracing/coresight/coresight-funnel.c.
>
> Mathieu, Mike, Suzuki, could you help confirm this is the right
> direction we should move forward to?
Leo, thanks for testing this out. Shiwanglai, please add Suzuki and
myself to future revision of this set - this will help you getting a
timely response for your work.
As Leo pointed out we already have support for replicators that don't
have a register map and the same thing should be done in this case.
But contrary to what was done for replicators, I think we should keep
the drivers in the same file as Russell did here[1]. That way we can
keep all things funnel at the same place and reduce the amount of
kernel configuration options.
Regards,
Mathieu
[1].
https://elixir.bootlin.com/linux/latest/source/drivers/tty/serial/amba-pl011.c#L2819
>
> ---8<---
> /* An invisible combo funnel between clusters and top funnel */
> funnel_combo {
> compatible = "arm,coresight-funnel";
> clocks = <_ctrl HI3660_PCLK>;
> clock-names = "apb_pclk";
>
> out-ports {
> port {
> combo_funnel_out: endpoint {
> remote-endpoint =
> <_funnel_in>;
> };
> };
> };
>
> in-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> reg = <0>;
> combo_funnel_in0: endpoint {
> remote-endpoint =
> <_etf_out>;
> };
> };
>
> port@1 {
> reg = <1>;
> combo_funnel_in1: endpoint {
> remote-endpoint =
> <_etf_out>;
> };
> };
> };
> };
>
> /* Top internals */
> funnel@ec031000 {
> compatible = "arm,coresight-funnel", "arm,primecell";
> reg = <0 0xec031000 0 0x1000>;
> clocks = <_ctrl HI3660_PCLK>;
> clock-names = "apb_pclk";
>
> out-ports {
>
Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
On Sat, Mar 02, 2019 at 09:45:22AM +, Shiwanglai wrote:
[...]
> > + /* Top internals */
> > + funnel@ec031000 {
> > + compatible = "arm,coresight-funnel", "arm,primecell";
> > + reg = <0 0xec031000 0 0x1000>;
> > + clocks = <_ctrl HI3660_PCLK>;
> > + clock-names = "apb_pclk";
> > +
> > + out-ports {
> > + port {
> > + top_funnel_out: endpoint {
> > + remote-endpoint =
> > + <_etf_in>;
> > + };
> > + };
> > + };
> > +
> > + in-ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + top_funnel_in0: endpoint {
> > + remote-endpoint =
> > + <_etf_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <0>;
>
> Here should s/<0>/<1>; otherwise DTC will complain warning for mismatching
> between 'port@1' and 'reg = <0>'.
> -- if reg set to 1, then there's no data output from cluster 1 to top.
Thanks for the info, Wanglai. Now I see why write as it is.
I can confirm if directly use your patch with perf with mainline
kernel I can capture CoreSight trace data successfully on Hikey960
board.
But since this DT binding will introduce DTC warning, I personally
think we can improve for this with below method:
We can create a funnel node named "funnel_combo", and we don't need to
specify register address range for it; and cluster 0 and cluster 1 will
output to "funnel_combo" and "funnel_combo" will output to the top
funnel. Thus the DT binding will write as below.
To support for a funnel without any register address range (we have
support replicator like this mode), we also need to extend the driver
drivers/hwtracing/coresight/coresight-funnel.c.
Mathieu, Mike, Suzuki, could you help confirm this is the right
direction we should move forward to?
---8<---
/* An invisible combo funnel between clusters and top funnel */
funnel_combo {
compatible = "arm,coresight-funnel";
clocks = <_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
out-ports {
port {
combo_funnel_out: endpoint {
remote-endpoint =
<_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
combo_funnel_in0: endpoint {
remote-endpoint =
<_etf_out>;
};
};
port@1 {
reg = <1>;
combo_funnel_in1: endpoint {
remote-endpoint =
<_etf_out>;
};
};
};
};
/* Top internals */
funnel@ec031000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xec031000 0 0x1000>;
clocks = <_ctrl HI3660_PCLK>;
clock-names = "apb_pclk";
out-ports {
port {
top_funnel_out: endpoint {
remote-endpoint =
<_etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
top_funnel_in: endpoint {
remote-endpoint =
<_funnel_out>;
};
};
};
};
--->8---
[...]
Thanks,
Leo Yan
Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
-邮件原件-
发件人: Leo Yan [mailto:leo@linaro.org]
发送时间: 2019年3月1日 15:33
收件人: Shiwanglai
抄送: robh...@kernel.org; mark.rutl...@arm.com; john.stu...@linaro.org; xuwei (O)
; linux-arm-ker...@lists.infradead.org;
devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
coresi...@lists.linaro.org; Suzhuangluan
主题: Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
Hi Wanglai,
On Thu, Feb 28, 2019 at 02:33:23PM +0800, Wanglai Shi wrote:
> This patch adds devicetree entries for the CoreSight trace components
> on hi3660.
>
> Signed-off-by: Wanglai Shi
> ---
> .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429
> +
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> 2 files changed, 431 insertions(+)
> create mode 100644
> arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> new file mode 100644
> index 000..d651a8b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/*
> + * dtsi for Hisilicon Hi3660 Coresight
> + *
> + * Copyright (C) 2016-2018 Hisilicon Ltd.
> + *
> + * Author: Wanglai Shi
> + *
> + */
> +/ {
> + soc {
> + /* A53 cluster internals */
> + etm@ecc4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecc4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@ecd4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecd4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@ece4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xece4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@ecf4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecf4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@ec801000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec801000 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> +
Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660
Hi Wanglai,
On Thu, Feb 28, 2019 at 02:33:23PM +0800, Wanglai Shi wrote:
> This patch adds devicetree entries for the CoreSight trace
> components on hi3660.
>
> Signed-off-by: Wanglai Shi
> ---
> .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429
> +
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> 2 files changed, 431 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> new file mode 100644
> index 000..d651a8b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/*
> + * dtsi for Hisilicon Hi3660 Coresight
> + *
> + * Copyright (C) 2016-2018 Hisilicon Ltd.
> + *
> + * Author: Wanglai Shi
> + *
> + */
> +/ {
> + soc {
> + /* A53 cluster internals */
> + etm@ecc4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecc4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@ecd4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecd4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@ece4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xece4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@ecf4 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecf4 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@ec801000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec801000 0 0x1000>;
> + clocks = <_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + cluster0_funnel_out: endpoint {
> + remote-endpoint =
> + <_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_in0: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> +
> + port@1 {
> +
[PATCH v2] dts: arm64: add CoreSight trace support for hi3660
This patch adds devicetree entries for the CoreSight trace
components on hi3660.
Signed-off-by: Wanglai Shi
---
.../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429 +
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
2 files changed, 431 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
new file mode 100644
index 000..d651a8b
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * dtsi for Hisilicon Hi3660 Coresight
+ *
+ * Copyright (C) 2016-2018 Hisilicon Ltd.
+ *
+ * Author: Wanglai Shi
+ *
+ */
+/ {
+ soc {
+ /* A53 cluster internals */
+ etm@ecc4 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecc4 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@ecd4 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecd4 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@ece4 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xece4 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@ecf4 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xecf4 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ cpu = <>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@ec801000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xec801000 0 0x1000>;
+ clocks = <_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ cluster0_funnel_out: endpoint {
+ remote-endpoint =
+ <_etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ cluster0_funnel_in0: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ cluster0_funnel_in1: endpoint {
+
