Re: [PATCH v2] of: update ePAPR references to point to Devicetree Specification

[Rob Herring]

On Thu, Jun 22, 2017 at 09:15:39AM -0700, frowand.l...@gmail.com wrote:
> From: Frank Rowand 
> 
> The Devicetree Specification has superseded the ePAPR as the
> base specification for bindings.  Update files in Documentation
> to reference the new document.
> 
> First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
> is generic, remove it.
> 
> Some files are not updated because there is no hypervisor chapter
> in the Devicetree Specification:
>Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
>Documenation/virtual/kvm/api.txt
>Documenation/virtual/kvm/ppc-pv.txt
> 
> Signed-off-by: Frank Rowand 
> ---
> 
> changes from v1:
>- remove boilerplat ePAPR reference from cci.txt
> 
>  Documentation/devicetree/bindings/arm/cci.txt | 15 
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt| 13 +++--
>  Documentation/devicetree/bindings/arm/idle-states.txt |  4 ++--
>  Documentation/devicetree/bindings/arm/l2c2x0.txt  |  4 ++--
>  Documentation/devicetree/bindings/arm/topology.txt|  4 ++--
>  Documentation/devicetree/bindings/bus/simple-pm-bus.txt   |  2 +-
>  Documentation/devicetree/bindings/chosen.txt  |  3 ++-
>  Documentation/devicetree/bindings/common-properties.txt   |  2 +-
>  Documentation/devicetree/bindings/crypto/fsl-sec4.txt |  4 ++--
>  Documentation/devicetree/bindings/crypto/fsl-sec6.txt |  4 ++--
>  .../devicetree/bindings/interrupt-controller/open-pic.txt |  5 ++---
>  Documentation/devicetree/bindings/net/ethernet.txt|  9 ++---
>  Documentation/devicetree/bindings/powerpc/fsl/cpus.txt|  6 +++---
>  Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt |  2 +-
>  .../devicetree/bindings/powerpc/fsl/srio-rmu.txt  |  4 ++--
>  Documentation/devicetree/bindings/powerpc/fsl/srio.txt|  3 ++-
>  Documentation/devicetree/booting-without-of.txt   |  2 +-
>  Documentation/devicetree/usage-model.txt  |  2 +-
>  Documentation/xtensa/mmu.txt  |  6 +++---
>  19 files changed, 46 insertions(+), 48 deletions(-)

Applied.

Re: [PATCH v2] of: update ePAPR references to point to Devicetree Specification

[Rob Herring]

On Thu, Jun 22, 2017 at 09:15:39AM -0700, frowand.l...@gmail.com wrote:
> From: Frank Rowand 
> 
> The Devicetree Specification has superseded the ePAPR as the
> base specification for bindings.  Update files in Documentation
> to reference the new document.
> 
> First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
> is generic, remove it.
> 
> Some files are not updated because there is no hypervisor chapter
> in the Devicetree Specification:
>Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
>Documenation/virtual/kvm/api.txt
>Documenation/virtual/kvm/ppc-pv.txt
> 
> Signed-off-by: Frank Rowand 
> ---
> 
> changes from v1:
>- remove boilerplat ePAPR reference from cci.txt
> 
>  Documentation/devicetree/bindings/arm/cci.txt | 15 
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt| 13 +++--
>  Documentation/devicetree/bindings/arm/idle-states.txt |  4 ++--
>  Documentation/devicetree/bindings/arm/l2c2x0.txt  |  4 ++--
>  Documentation/devicetree/bindings/arm/topology.txt|  4 ++--
>  Documentation/devicetree/bindings/bus/simple-pm-bus.txt   |  2 +-
>  Documentation/devicetree/bindings/chosen.txt  |  3 ++-
>  Documentation/devicetree/bindings/common-properties.txt   |  2 +-
>  Documentation/devicetree/bindings/crypto/fsl-sec4.txt |  4 ++--
>  Documentation/devicetree/bindings/crypto/fsl-sec6.txt |  4 ++--
>  .../devicetree/bindings/interrupt-controller/open-pic.txt |  5 ++---
>  Documentation/devicetree/bindings/net/ethernet.txt|  9 ++---
>  Documentation/devicetree/bindings/powerpc/fsl/cpus.txt|  6 +++---
>  Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt |  2 +-
>  .../devicetree/bindings/powerpc/fsl/srio-rmu.txt  |  4 ++--
>  Documentation/devicetree/bindings/powerpc/fsl/srio.txt|  3 ++-
>  Documentation/devicetree/booting-without-of.txt   |  2 +-
>  Documentation/devicetree/usage-model.txt  |  2 +-
>  Documentation/xtensa/mmu.txt  |  6 +++---
>  19 files changed, 46 insertions(+), 48 deletions(-)

Applied.

[PATCH v2] of: update ePAPR references to point to Devicetree Specification

[frowand . list]

From: Frank Rowand 

The Devicetree Specification has superseded the ePAPR as the
base specification for bindings.  Update files in Documentation
to reference the new document.

First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.

Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
   Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
   Documenation/virtual/kvm/api.txt
   Documenation/virtual/kvm/ppc-pv.txt

Signed-off-by: Frank Rowand 
---

changes from v1:
   - remove boilerplat ePAPR reference from cci.txt

 Documentation/devicetree/bindings/arm/cci.txt | 15 ---
 Documentation/devicetree/bindings/arm/cpus.txt| 13 +++--
 Documentation/devicetree/bindings/arm/idle-states.txt |  4 ++--
 Documentation/devicetree/bindings/arm/l2c2x0.txt  |  4 ++--
 Documentation/devicetree/bindings/arm/topology.txt|  4 ++--
 Documentation/devicetree/bindings/bus/simple-pm-bus.txt   |  2 +-
 Documentation/devicetree/bindings/chosen.txt  |  3 ++-
 Documentation/devicetree/bindings/common-properties.txt   |  2 +-
 Documentation/devicetree/bindings/crypto/fsl-sec4.txt |  4 ++--
 Documentation/devicetree/bindings/crypto/fsl-sec6.txt |  4 ++--
 .../devicetree/bindings/interrupt-controller/open-pic.txt |  5 ++---
 Documentation/devicetree/bindings/net/ethernet.txt|  9 ++---
 Documentation/devicetree/bindings/powerpc/fsl/cpus.txt|  6 +++---
 Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt |  2 +-
 .../devicetree/bindings/powerpc/fsl/srio-rmu.txt  |  4 ++--
 Documentation/devicetree/bindings/powerpc/fsl/srio.txt|  3 ++-
 Documentation/devicetree/booting-without-of.txt   |  2 +-
 Documentation/devicetree/usage-model.txt  |  2 +-
 Documentation/xtensa/mmu.txt  |  6 +++---
 19 files changed, 46 insertions(+), 48 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cci.txt 
b/Documentation/devicetree/bindings/arm/cci.txt
index 0f2153e8fa7e..9600761f2d5b 100644
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global 
control register
 space and multiple sets of interface control registers, one per slave
 interface.
 
-Bindings for the CCI node follow the ePAPR standard, available from:
-
-www.power.org/documentation/epapr-version-1-1/
-
-with the addition of the bindings described in this document which are
-specific to ARM.
-
 * CCI interconnect node
 
Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM.
as a tuple of cells, containing child address,
parent address and the size of the region in the
child address space.
-   Definition: A standard property. Follow rules in the ePAPR for
-   hierarchical bus addressing. CCI interfaces
-   addresses refer to the parent node addressing
-   scheme to declare their register bases.
+   Definition: A standard property. Follow rules in the Devicetree
+   Specification for hierarchical bus addressing. CCI
+   interfaces addresses refer to the parent node
+   addressing scheme to declare their register bases.
 
CCI interconnect node can define the following child nodes:
 
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 1030f5f50207..283c520a2224 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a 
system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+Bindings for CPU nodes follow the Devicetree Specification, available from:
 
-https://www.power.org/documentation/epapr-version-1-1/
+https://www.devicetree.org/specifications/
 
 with updates for 32-bit and 64-bit ARM systems provided in this document.
 
@@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in 
this document.
 Convention used in this document
 
 
-This document follows the conventions described in the ePAPR v1.1, with
-the addition:
+This document follows the conventions described in the Devicetree
+Specification, with the addition:
 
 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
   the reg property contained in bits 7 down to 0
@@ -26,8 +26,9 @@ the 

[PATCH v2] of: update ePAPR references to point to Devicetree Specification

[frowand . list]

From: Frank Rowand 

The Devicetree Specification has superseded the ePAPR as the
base specification for bindings.  Update files in Documentation
to reference the new document.

First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.

Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
   Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
   Documenation/virtual/kvm/api.txt
   Documenation/virtual/kvm/ppc-pv.txt

Signed-off-by: Frank Rowand 
---

changes from v1:
   - remove boilerplat ePAPR reference from cci.txt

 Documentation/devicetree/bindings/arm/cci.txt | 15 ---
 Documentation/devicetree/bindings/arm/cpus.txt| 13 +++--
 Documentation/devicetree/bindings/arm/idle-states.txt |  4 ++--
 Documentation/devicetree/bindings/arm/l2c2x0.txt  |  4 ++--
 Documentation/devicetree/bindings/arm/topology.txt|  4 ++--
 Documentation/devicetree/bindings/bus/simple-pm-bus.txt   |  2 +-
 Documentation/devicetree/bindings/chosen.txt  |  3 ++-
 Documentation/devicetree/bindings/common-properties.txt   |  2 +-
 Documentation/devicetree/bindings/crypto/fsl-sec4.txt |  4 ++--
 Documentation/devicetree/bindings/crypto/fsl-sec6.txt |  4 ++--
 .../devicetree/bindings/interrupt-controller/open-pic.txt |  5 ++---
 Documentation/devicetree/bindings/net/ethernet.txt|  9 ++---
 Documentation/devicetree/bindings/powerpc/fsl/cpus.txt|  6 +++---
 Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt |  2 +-
 .../devicetree/bindings/powerpc/fsl/srio-rmu.txt  |  4 ++--
 Documentation/devicetree/bindings/powerpc/fsl/srio.txt|  3 ++-
 Documentation/devicetree/booting-without-of.txt   |  2 +-
 Documentation/devicetree/usage-model.txt  |  2 +-
 Documentation/xtensa/mmu.txt  |  6 +++---
 19 files changed, 46 insertions(+), 48 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cci.txt 
b/Documentation/devicetree/bindings/arm/cci.txt
index 0f2153e8fa7e..9600761f2d5b 100644
--- a/Documentation/devicetree/bindings/arm/cci.txt
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global 
control register
 space and multiple sets of interface control registers, one per slave
 interface.
 
-Bindings for the CCI node follow the ePAPR standard, available from:
-
-www.power.org/documentation/epapr-version-1-1/
-
-with the addition of the bindings described in this document which are
-specific to ARM.
-
 * CCI interconnect node
 
Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM.
as a tuple of cells, containing child address,
parent address and the size of the region in the
child address space.
-   Definition: A standard property. Follow rules in the ePAPR for
-   hierarchical bus addressing. CCI interfaces
-   addresses refer to the parent node addressing
-   scheme to declare their register bases.
+   Definition: A standard property. Follow rules in the Devicetree
+   Specification for hierarchical bus addressing. CCI
+   interfaces addresses refer to the parent node
+   addressing scheme to declare their register bases.
 
CCI interconnect node can define the following child nodes:
 
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 1030f5f50207..283c520a2224 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a 
system through
 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
 defining properties for every cpu.
 
-Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
+Bindings for CPU nodes follow the Devicetree Specification, available from:
 
-https://www.power.org/documentation/epapr-version-1-1/
+https://www.devicetree.org/specifications/
 
 with updates for 32-bit and 64-bit ARM systems provided in this document.
 
@@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in 
this document.
 Convention used in this document
 
 
-This document follows the conventions described in the ePAPR v1.1, with
-the addition:
+This document follows the conventions described in the Devicetree
+Specification, with the addition:
 
 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
   the reg property contained in bits 7 down to 0
@@ -26,8 +26,9 @@ the addition:
 cpus and cpu node bindings definition