Re: [PATCH v2] usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC

[Singh, Sandeep]

On 10/26/2020 8:16 PM, Mathias Nyman wrote:

[CAUTION: External Email]

On 23.10.2020 16.15, Sandeep Singh wrote:

From: Sandeep Singh 

On some platform of AMD, S3 fails with HCE and SRE errors. To fix this,
need to disable a bit which is enable in sparse controller.

Signed-off-by: Sanket Goswami 
Signed-off-by: Sandeep Singh 
---
Changes since 
v1:(https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.org%2Flkml%2F2020%2F10%2F23%2F368data=04%7C01%7CSandeep.Singh%40amd.com%7Ca8900bc99ca441507cc408d879bdc5e9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637393203258053573%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=GM7TXOawh6nLZaX1ABZLlptYeyoUSMHnwhCxbY6zFZI%3Dreserved=0)
   -> Add xhci.h changes


Added to queue.
This looks like it should go to stable as well.


Thanks Mathias , please help to queue this up from 4.19+.

Regards

Sandeep



-Mathias

Re: [PATCH v2] usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC

[Mathias Nyman]

On 23.10.2020 16.15, Sandeep Singh wrote:
> From: Sandeep Singh 
> 
> On some platform of AMD, S3 fails with HCE and SRE errors. To fix this,
> need to disable a bit which is enable in sparse controller.
> 
> Signed-off-by: Sanket Goswami 
> Signed-off-by: Sandeep Singh 
> ---
> Changes since v1:(https://lkml.org/lkml/2020/10/23/368)
>   -> Add xhci.h changes
> 

Added to queue.
This looks like it should go to stable as well.

-Mathias

[PATCH v2] usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC

[Sandeep Singh]

From: Sandeep Singh 

On some platform of AMD, S3 fails with HCE and SRE errors. To fix this,
need to disable a bit which is enable in sparse controller.

Signed-off-by: Sanket Goswami 
Signed-off-by: Sandeep Singh 
---
Changes since v1:(https://lkml.org/lkml/2020/10/23/368)
-> Add xhci.h changes

 drivers/usb/host/xhci-pci.c | 17 +
 drivers/usb/host/xhci.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index c26c06e5c88c..bf89172c43ca 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -23,6 +23,8 @@
 #define SSIC_PORT_CFG2_OFFSET  0x30
 #define PROG_DONE  (1 << 30)
 #define SSIC_PORT_UNUSED   (1 << 31)
+#define SPARSE_DISABLE_BIT 17
+#define SPARSE_CNTL_ENABLE 0xC12C
 
 /* Device for a quirk */
 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
@@ -161,6 +163,9 @@ static void xhci_pci_quirks(struct device *dev, struct 
xhci_hcd *xhci)
(pdev->device == 0x15e0 || pdev->device == 0x15e1))
xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 
+   if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
+   xhci->quirks |= XHCI_DISABLE_SPARSE;
+
if (pdev->vendor == PCI_VENDOR_ID_AMD)
xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
@@ -498,6 +503,15 @@ static void xhci_pme_quirk(struct usb_hcd *hcd)
readl(reg);
 }
 
+static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
+{
+   u32 reg;
+
+   reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
+   reg &= ~BIT(SPARSE_DISABLE_BIT);
+   writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
+}
+
 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
@@ -517,6 +531,9 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool 
do_wakeup)
if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
xhci_ssic_port_unused_quirk(hcd, true);
 
+   if (xhci->quirks & XHCI_DISABLE_SPARSE)
+   xhci_sparse_control_quirk(hcd);
+
ret = xhci_suspend(xhci, do_wakeup);
if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
xhci_ssic_port_unused_quirk(hcd, false);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 8be88379c0fb..ebb359ebb261 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1877,6 +1877,7 @@ struct xhci_hcd {
 #define XHCI_SNPS_BROKEN_SUSPENDBIT_ULL(35)
 #define XHCI_RENESAS_FW_QUIRK  BIT_ULL(36)
 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
+#define XHCI_DISABLE_SPARSEBIT_ULL(38)
 
unsigned intnum_active_eps;
unsigned intlimit_active_eps;
-- 
2.25.1