Re: [PATCH v2 0/3] Get cache information from userland
On Thu, 27 Aug 2020 01:22:25 PDT (-0700), zong...@sifive.com wrote: There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. We exploit 'struct cacheinfo' to obtain the information of cache, then we don't need additional variable or data structure to record it. We also need some works in glibc, but we have to support the function in kernel first by rule of glibc, then post the patch to glibc site. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Changed in v2: - Add error checking for parsing cache properties. Zong Li (3): riscv: Set more data to cacheinfo riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO riscv: Add cache information in AUX vector arch/riscv/include/asm/cacheinfo.h | 5 ++ arch/riscv/include/asm/elf.h | 13 arch/riscv/include/uapi/asm/auxvec.h | 24 arch/riscv/kernel/cacheinfo.c| 91 +++- 4 files changed, 117 insertions(+), 16 deletions(-) Thanks, these are on for-next.
[PATCH v2 0/3] Get cache information from userland
There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. We exploit 'struct cacheinfo' to obtain the information of cache, then we don't need additional variable or data structure to record it. We also need some works in glibc, but we have to support the function in kernel first by rule of glibc, then post the patch to glibc site. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Changed in v2: - Add error checking for parsing cache properties. Zong Li (3): riscv: Set more data to cacheinfo riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO riscv: Add cache information in AUX vector arch/riscv/include/asm/cacheinfo.h | 5 ++ arch/riscv/include/asm/elf.h | 13 arch/riscv/include/uapi/asm/auxvec.h | 24 arch/riscv/kernel/cacheinfo.c| 91 +++- 4 files changed, 117 insertions(+), 16 deletions(-) -- 2.28.0
