Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, 2018-08-27 at 17:50 +0200, Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on > > > Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, > > > and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update > > > the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 > > and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get > > the > > following message (mmc0 being the SDHCI instance of one of them SD > > card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 > > being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 > > Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, 2018-08-27 at 17:50 +0200, Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on > > > Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, > > > and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update > > > the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 > > and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get > > the > > following message (mmc0 being the SDHCI instance of one of them SD > > card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 > > being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 > > Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, 27 Aug 2018 17:50:53 +0200 Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get the > > following message (mmc0 being the SDHCI instance of one of them SD card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal voltage: 1 (1.80 V) > > driver
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, 27 Aug 2018 17:50:53 +0200 Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get the > > following message (mmc0 being the SDHCI instance of one of them SD card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal voltage: 1 (1.80 V) > > driver
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, Aug 27, 2018 at 05:50:53PM +0200, Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get the > > following message (mmc0 being the SDHCI instance of one of them SD card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal voltage: 1 (1.80 V) > > driver
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, Aug 27, 2018 at 05:50:53PM +0200, Thierry Reding wrote: > On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > > Hi all, > > > > > > This series implements support for faster signaling modes on Tegra > > > SDHCI controllers. This series consist of several parts: changes > > > requried for 1.8 V signaling and pad control, pad calibration, and > > > tuning. Following earlies patch sets have been merged into this > > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > > enable > > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > > padautocal procedure". Also the patches for enabling SDHCI tuning > > > are added. > > > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > > Apalis TK1. It at least does not seem to make things any worse but > > HS200 on TK1 still seems to behave strangely. During boot I do get the > > following message (mmc0 being the SDHCI instance of one of them SD card > > slots): > > > > [3.238360] mmc0: Internal clock never stabilised. > > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > > === > > [3.249649] mmc0: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > > cnt: 0x > > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > > 0x > > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x > > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > > gap: 0x > > [3.282041] mmc0: sdhci: Wake-up: 0x | > > Clock:0x0401 > > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > > 0x > > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > > 0x00fc0003 > > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > > 0x > > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > > 0x > > [3.321159] mmc0: sdhci: Resp[0]: 0x | > > Resp[1]: 0x > > [3.327642] mmc0: sdhci: Resp[2]: 0x | > > Resp[3]: 0x > > [3.334144] mmc0: sdhci: Host ctl2: 0x > > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0x > > [3.345110] mmc0: sdhci: > > > > > > And it subsequently stalls waiting for interrupt for more than 8 > > seconds before continuing to mount the rootfs as follows (mmc2 being > > the SDHCI instance of the eMMC): > > > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > > at 29700 Hz pixel clock > > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > > === > > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > > Version: 0x0303 > > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > > cnt: 0x0001 > > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > > 0x0013 > > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > > 0x0031 > > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > > gap: 0x > > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > > Clock:0x0007 > > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > > 0x > > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > > 0x02fc000b > > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > > 0x > > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > > Caps_1: 0x1f70 > > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > > 0x > > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > > Resp[1]: 0x048062bf > > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > > Resp[3]: 0x0240 > > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > > 0xfbc6b208 > > [ 14.036561] mmc2: sdhci: > > > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > > chardev (247:0) > > [ 14.078260] mmcblk2: p1 p2 > > > > After that it actually seems to work quite nicely: > > > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > > clock: 2 Hz > > actual clock: 16320 Hz > > vdd:21 (3.3 ~ 3.4 V) > > bus mode: 2 (push-pull) > > chip select:0 (don't care) > > power mode: 2 (on) > > bus width: 3 (8 bits) > > timing spec:9 (mmc HS200) > > signal voltage: 1 (1.80 V) > > driver
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > Hi all, > > > > This series implements support for faster signaling modes on Tegra > > SDHCI controllers. This series consist of several parts: changes > > requried for 1.8 V signaling and pad control, pad calibration, and > > tuning. Following earlies patch sets have been merged into this > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > enable > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > padautocal procedure". Also the patches for enabling SDHCI tuning > > are added. > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > Apalis TK1. It at least does not seem to make things any worse but > HS200 on TK1 still seems to behave strangely. During boot I do get the > following message (mmc0 being the SDHCI instance of one of them SD card > slots): > > [3.238360] mmc0: Internal clock never stabilised. > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > === > [3.249649] mmc0: sdhci: Sys addr: 0x | > Version: 0x0303 > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > cnt: 0x > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > 0x > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > 0x > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > gap: 0x > [3.282041] mmc0: sdhci: Wake-up: 0x | > Clock:0x0401 > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > 0x > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > 0x00fc0003 > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > 0x > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > Caps_1: 0x1f70 > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > 0x > [3.321159] mmc0: sdhci: Resp[0]: 0x | > Resp[1]: 0x > [3.327642] mmc0: sdhci: Resp[2]: 0x | > Resp[3]: 0x > [3.334144] mmc0: sdhci: Host ctl2: 0x > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > 0x > [3.345110] mmc0: sdhci: > > > And it subsequently stalls waiting for interrupt for more than 8 > seconds before continuing to mount the rootfs as follows (mmc2 being > the SDHCI instance of the eMMC): > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > at 29700 Hz pixel clock > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > === > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > Version: 0x0303 > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > cnt: 0x0001 > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > 0x0013 > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > 0x0031 > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > gap: 0x > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > Clock:0x0007 > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > 0x > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > 0x02fc000b > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > 0x > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > Caps_1: 0x1f70 > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > 0x > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > Resp[1]: 0x048062bf > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > Resp[3]: 0x0240 > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > 0xfbc6b208 > [ 14.036561] mmc2: sdhci: > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > chardev (247:0) > [ 14.078260] mmcblk2: p1 p2 > > After that it actually seems to work quite nicely: > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > clock: 2 Hz > actual clock: 16320 Hz > vdd:21 (3.3 ~ 3.4 V) > bus mode: 2 (push-pull) > chip select:0 (don't care) > power mode: 2 (on) > bus width: 3 (8 bits) > timing spec:9 (mmc HS200) > signal voltage: 1 (1.80 V) > driver type:0 (driver type B) > root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 > > /dev/mmcblk2: > Timing buffered disk reads: 408 MB in 3.01 seconds = 135.39 MB/sec > > Have you ever observed similar behaviour? What could cause this? > > Anybody else tried it on TK1? I can't reproduce this
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Mon, Aug 27, 2018 at 02:10:58PM +, Marcel Ziswiler wrote: > On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > > Hi all, > > > > This series implements support for faster signaling modes on Tegra > > SDHCI controllers. This series consist of several parts: changes > > requried for 1.8 V signaling and pad control, pad calibration, and > > tuning. Following earlies patch sets have been merged into this > > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > > enable > > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > > padautocal procedure". Also the patches for enabling SDHCI tuning > > are added. > > I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and > Apalis TK1. It at least does not seem to make things any worse but > HS200 on TK1 still seems to behave strangely. During boot I do get the > following message (mmc0 being the SDHCI instance of one of them SD card > slots): > > [3.238360] mmc0: Internal clock never stabilised. > [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP > === > [3.249649] mmc0: sdhci: Sys addr: 0x | > Version: 0x0303 > [3.256138] mmc0: sdhci: Blk size: 0x | Blk > cnt: 0x > [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: > 0x > [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: > 0x > [3.275580] mmc0: sdhci: Power: 0x000f | Blk > gap: 0x > [3.282041] mmc0: sdhci: Wake-up: 0x | > Clock:0x0401 > [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: > 0x > [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: > 0x00fc0003 > [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: > 0x > [3.308022] mmc0: sdhci: Caps: 0x376fd080 | > Caps_1: 0x1f70 > [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: > 0x > [3.321159] mmc0: sdhci: Resp[0]: 0x | > Resp[1]: 0x > [3.327642] mmc0: sdhci: Resp[2]: 0x | > Resp[3]: 0x > [3.334144] mmc0: sdhci: Host ctl2: 0x > [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: > 0x > [3.345110] mmc0: sdhci: > > > And it subsequently stalls waiting for interrupt for more than 8 > seconds before continuing to mount the rootfs as follows (mmc2 being > the SDHCI instance of the eMMC): > > [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz > at 29700 Hz pixel clock > [ 13.930136] mmc2: Timeout waiting for hardware interrupt. > [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP > === > [ 13.942071] mmc2: sdhci: Sys addr: 0x | > Version: 0x0303 > [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk > cnt: 0x0001 > [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: > 0x0013 > [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: > 0x0031 > [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk > gap: 0x > [ 13.974263] mmc2: sdhci: Wake-up: 0x | > Clock:0x0007 > [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: > 0x > [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: > 0x02fc000b > [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: > 0x > [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | > Caps_1: 0x1f70 > [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: > 0x > [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | > Resp[1]: 0x048062bf > [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | > Resp[3]: 0x0240 > [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b > [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: > 0xfbc6b208 > [ 14.036561] mmc2: sdhci: > > [ 14.044332] mmc2: new HS200 MMC card at address 0001 > [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB > [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB > [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB > [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, > chardev (247:0) > [ 14.078260] mmcblk2: p1 p2 > > After that it actually seems to work quite nicely: > > root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios > clock: 2 Hz > actual clock: 16320 Hz > vdd:21 (3.3 ~ 3.4 V) > bus mode: 2 (push-pull) > chip select:0 (don't care) > power mode: 2 (on) > bus width: 3 (8 bits) > timing spec:9 (mmc HS200) > signal voltage: 1 (1.80 V) > driver type:0 (driver type B) > root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 > > /dev/mmcblk2: > Timing buffered disk reads: 408 MB in 3.01 seconds = 135.39 MB/sec > > Have you ever observed similar behaviour? What could cause this? > > Anybody else tried it on TK1? I can't reproduce this
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and Apalis TK1. It at least does not seem to make things any worse but HS200 on TK1 still seems to behave strangely. During boot I do get the following message (mmc0 being the SDHCI instance of one of them SD card slots): [3.238360] mmc0: Internal clock never stabilised. [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP === [3.249649] mmc0: sdhci: Sys addr: 0x | Version: 0x0303 [3.256138] mmc0: sdhci: Blk size: 0x | Blk cnt: 0x [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: 0x [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: 0x [3.275580] mmc0: sdhci: Power: 0x000f | Blk gap: 0x [3.282041] mmc0: sdhci: Wake-up: 0x | Clock:0x0401 [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: 0x [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: 0x00fc0003 [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: 0x [3.308022] mmc0: sdhci: Caps: 0x376fd080 | Caps_1: 0x1f70 [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: 0x [3.321159] mmc0: sdhci: Resp[0]: 0x | Resp[1]: 0x [3.327642] mmc0: sdhci: Resp[2]: 0x | Resp[3]: 0x [3.334144] mmc0: sdhci: Host ctl2: 0x [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: 0x [3.345110] mmc0: sdhci: And it subsequently stalls waiting for interrupt for more than 8 seconds before continuing to mount the rootfs as follows (mmc2 being the SDHCI instance of the eMMC): [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz at 29700 Hz pixel clock [ 13.930136] mmc2: Timeout waiting for hardware interrupt. [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP === [ 13.942071] mmc2: sdhci: Sys addr: 0x | Version: 0x0303 [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk cnt: 0x0001 [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: 0x0013 [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: 0x0031 [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk gap: 0x [ 13.974263] mmc2: sdhci: Wake-up: 0x | Clock:0x0007 [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: 0x [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: 0x02fc000b [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: 0x [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | Caps_1: 0x1f70 [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: 0x [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | Resp[1]: 0x048062bf [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | Resp[3]: 0x0240 [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: 0xfbc6b208 [ 14.036561] mmc2: sdhci: [ 14.044332] mmc2: new HS200 MMC card at address 0001 [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, chardev (247:0) [ 14.078260] mmcblk2: p1 p2 After that it actually seems to work quite nicely: root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios clock: 2 Hz actual clock: 16320 Hz vdd:21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select:0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec:9 (mmc HS200) signal voltage: 1 (1.80 V) driver type:0 (driver type B) root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 408 MB in 3.01 seconds = 135.39 MB/sec Have you ever observed similar behaviour? What could cause this? Anybody else tried it on TK1?
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, 2018-08-10 at 21:08 +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI > enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. I tried your tkln/hs200 branch on Colibri T20, Apalis/Colibri T30 and Apalis TK1. It at least does not seem to make things any worse but HS200 on TK1 still seems to behave strangely. During boot I do get the following message (mmc0 being the SDHCI instance of one of them SD card slots): [3.238360] mmc0: Internal clock never stabilised. [3.243183] mmc0: sdhci: SDHCI REGISTER DUMP === [3.249649] mmc0: sdhci: Sys addr: 0x | Version: 0x0303 [3.256138] mmc0: sdhci: Blk size: 0x | Blk cnt: 0x [3.262657] mmc0: sdhci: Argument: 0x | Trn mode: 0x [3.269119] mmc0: sdhci: Present: 0x01fb00f0 | Host ctl: 0x [3.275580] mmc0: sdhci: Power: 0x000f | Blk gap: 0x [3.282041] mmc0: sdhci: Wake-up: 0x | Clock:0x0401 [3.288485] mmc0: sdhci: Timeout: 0x | Int stat: 0x [3.295037] mmc0: sdhci: Int enab: 0x00ff0003 | Sig enab: 0x00fc0003 [3.301559] mmc0: sdhci: AC12 err: 0x | Slot int: 0x [3.308022] mmc0: sdhci: Caps: 0x376fd080 | Caps_1: 0x1f70 [3.314527] mmc0: sdhci: Cmd: 0x | Max curr: 0x [3.321159] mmc0: sdhci: Resp[0]: 0x | Resp[1]: 0x [3.327642] mmc0: sdhci: Resp[2]: 0x | Resp[3]: 0x [3.334144] mmc0: sdhci: Host ctl2: 0x [3.338613] mmc0: sdhci: ADMA Err: 0x | ADMA Ptr: 0x [3.345110] mmc0: sdhci: And it subsequently stalls waiting for interrupt for more than 8 seconds before continuing to mount the rootfs as follows (mmc2 being the SDHCI instance of the eMMC): [4.874017] tegra-hdmi 5428.hdmi: cannot set audio to 48000 Hz at 29700 Hz pixel clock [ 13.930136] mmc2: Timeout waiting for hardware interrupt. [ 13.935603] mmc2: sdhci: SDHCI REGISTER DUMP === [ 13.942071] mmc2: sdhci: Sys addr: 0x | Version: 0x0303 [ 13.948511] mmc2: sdhci: Blk size: 0x7080 | Blk cnt: 0x0001 [ 13.954948] mmc2: sdhci: Argument: 0x | Trn mode: 0x0013 [ 13.961385] mmc2: sdhci: Present: 0x01fb00f0 | Host ctl: 0x0031 [ 13.967821] mmc2: sdhci: Power: 0x0001 | Blk gap: 0x [ 13.974263] mmc2: sdhci: Wake-up: 0x | Clock:0x0007 [ 13.980692] mmc2: sdhci: Timeout: 0x000e | Int stat: 0x [ 13.987119] mmc2: sdhci: Int enab: 0x02ff000b | Sig enab: 0x02fc000b [ 13.993546] mmc2: sdhci: AC12 err: 0x | Slot int: 0x [ 13.74] mmc2: sdhci: Caps: 0x376fd080 | Caps_1: 0x1f70 [ 14.006415] mmc2: sdhci: Cmd: 0x153a | Max curr: 0x [ 14.012845] mmc2: sdhci: Resp[0]: 0x0b00 | Resp[1]: 0x048062bf [ 14.019272] mmc2: sdhci: Resp[2]: 0x314a8000 | Resp[3]: 0x0240 [ 14.025697] mmc2: sdhci: Host ctl2: 0x000b [ 14.030132] mmc2: sdhci: ADMA Err: 0x | ADMA Ptr: 0xfbc6b208 [ 14.036561] mmc2: sdhci: [ 14.044332] mmc2: new HS200 MMC card at address 0001 [ 14.050656] mmcblk2: mmc2:0001 016G30 14.7 GiB [ 14.056376] mmcblk2boot0: mmc2:0001 016G30 partition 1 4.00 MiB [ 14.063563] mmcblk2boot1: mmc2:0001 016G30 partition 2 4.00 MiB [ 14.069589] mmcblk2rpmb: mmc2:0001 016G30 partition 3 4.00 MiB, chardev (247:0) [ 14.078260] mmcblk2: p1 p2 After that it actually seems to work quite nicely: root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios clock: 2 Hz actual clock: 16320 Hz vdd:21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select:0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec:9 (mmc HS200) signal voltage: 1 (1.80 V) driver type:0 (driver type B) root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 408 MB in 3.01 seconds = 135.39 MB/sec Have you ever observed similar behaviour? What could cause this? Anybody else tried it on TK1?
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 27/08/18 13:26, Adrian Hunter wrote: > On 27/08/18 13:10, Thierry Reding wrote: >> On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >>> Hi all, >>> >>> This series implements support for faster signaling modes on Tegra >>> SDHCI controllers. This series consist of several parts: changes >>> requried for 1.8 V signaling and pad control, pad calibration, and >>> tuning. Following earlies patch sets have been merged into this >>> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >>> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >>> padautocal procedure". Also the patches for enabling SDHCI tuning >>> are added. >>> >>> Changelog: >>> v2: >>> - Fix grammar in PMC device tree bindings docs >>> - Remove a stray line from tegra sdhci bindings >>> - Cosmetic changes to PMC pinctrl driver >>> - Fix a typo in "soc/tegra: pmc: Implement >>> tegra_io_pad_is_powered()" commit message >>> - Declare mask and value on the same line in >>> tegra_io_pad_is_powered() >>> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >>> inside the if condition in tegra_sdhci_reset() >>> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >>> - Move sdhci_writel() out of the enable if-else body in >>> tegra_sdhci_configure_cal_pad() >>> - Add a delay before starting polling in >>> tegra_sdhci_pad_autocalib() >>> - Use usleep_range() in tegra_sdhci_set_tap() >>> - Rename orig_enabled to status in >>> tegra_sdhci_configure_card_clk() >>> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >>> >>> v1: >>> - Probe the regulator voltage capabilities to determine whether pinctrl >>> is needed in tegra_sdhci_r eset >>> - Don't remove tegra_sdhci_voltage_switch() >>> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >>> - Don't change start_signal_voltage_switch callback if pinctrl info >>> invalid >>> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >>> - Add nvidia, prefix to pad autocal offset dt props in the example >>> >>> See the original patch sets for earlier changelogs. >>> >>> Aapo Vienamo (40): >>> dt-bindings: Add Tegra PMC pad configuration bindings >>> dt-bindings: mmc: tegra: Add pad voltage control properties >>> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >>> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >>> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >>> soc/tegra: pmc: Factor out DPD register bit calculation >>> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >>> soc/tegra: pmc: Use X macro to generate IO pad tables >>> soc/tegra: pmc: Remove public pad voltage APIs >>> soc/tegra: pmc: Implement pad configuration via pinctrl >>> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >>> tuning >>> mmc: tegra: Reconfigure pad voltages during voltage switching >>> mmc: tegra: Poll for calibration completion >>> mmc: tegra: Set calibration pad voltage reference >>> mmc: tegra: Power on the calibration pad >>> mmc: tegra: Disable card clock during pad calibration >>> mmc: tegra: Program pad autocal offsets from dt >>> mmc: tegra: Perform pad calibration after voltage switch >>> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >>> mmc: tegra: Add a workaround for tap value change glitch >>> mmc: tegra: Parse default trim and tap from dt >>> mmc: tegra: Configure default tap values >>> mmc: tegra: Configure default trim value on reset >>> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >>> mmc: sdhci: Add a quirk to disable card clock during tuning >>> mmc: tegra: Enable workaround for tuning transfer mode bug >>> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >>> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >>> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >>> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >>> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >>> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >>> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >>> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >>> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >>> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >>> arm64: dts: tegra210: Add SDHCI tap and trim values >>> arm64: dts: tegra186: Add SDHCI tap and trim values >>> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >>> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >>> >>> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >>> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >>> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >>>
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 27/08/18 13:26, Adrian Hunter wrote: > On 27/08/18 13:10, Thierry Reding wrote: >> On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >>> Hi all, >>> >>> This series implements support for faster signaling modes on Tegra >>> SDHCI controllers. This series consist of several parts: changes >>> requried for 1.8 V signaling and pad control, pad calibration, and >>> tuning. Following earlies patch sets have been merged into this >>> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >>> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >>> padautocal procedure". Also the patches for enabling SDHCI tuning >>> are added. >>> >>> Changelog: >>> v2: >>> - Fix grammar in PMC device tree bindings docs >>> - Remove a stray line from tegra sdhci bindings >>> - Cosmetic changes to PMC pinctrl driver >>> - Fix a typo in "soc/tegra: pmc: Implement >>> tegra_io_pad_is_powered()" commit message >>> - Declare mask and value on the same line in >>> tegra_io_pad_is_powered() >>> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >>> inside the if condition in tegra_sdhci_reset() >>> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >>> - Move sdhci_writel() out of the enable if-else body in >>> tegra_sdhci_configure_cal_pad() >>> - Add a delay before starting polling in >>> tegra_sdhci_pad_autocalib() >>> - Use usleep_range() in tegra_sdhci_set_tap() >>> - Rename orig_enabled to status in >>> tegra_sdhci_configure_card_clk() >>> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >>> >>> v1: >>> - Probe the regulator voltage capabilities to determine whether pinctrl >>> is needed in tegra_sdhci_r eset >>> - Don't remove tegra_sdhci_voltage_switch() >>> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >>> - Don't change start_signal_voltage_switch callback if pinctrl info >>> invalid >>> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >>> - Add nvidia, prefix to pad autocal offset dt props in the example >>> >>> See the original patch sets for earlier changelogs. >>> >>> Aapo Vienamo (40): >>> dt-bindings: Add Tegra PMC pad configuration bindings >>> dt-bindings: mmc: tegra: Add pad voltage control properties >>> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >>> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >>> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >>> soc/tegra: pmc: Factor out DPD register bit calculation >>> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >>> soc/tegra: pmc: Use X macro to generate IO pad tables >>> soc/tegra: pmc: Remove public pad voltage APIs >>> soc/tegra: pmc: Implement pad configuration via pinctrl >>> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >>> tuning >>> mmc: tegra: Reconfigure pad voltages during voltage switching >>> mmc: tegra: Poll for calibration completion >>> mmc: tegra: Set calibration pad voltage reference >>> mmc: tegra: Power on the calibration pad >>> mmc: tegra: Disable card clock during pad calibration >>> mmc: tegra: Program pad autocal offsets from dt >>> mmc: tegra: Perform pad calibration after voltage switch >>> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >>> mmc: tegra: Add a workaround for tap value change glitch >>> mmc: tegra: Parse default trim and tap from dt >>> mmc: tegra: Configure default tap values >>> mmc: tegra: Configure default trim value on reset >>> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >>> mmc: sdhci: Add a quirk to disable card clock during tuning >>> mmc: tegra: Enable workaround for tuning transfer mode bug >>> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >>> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >>> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >>> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >>> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >>> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >>> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >>> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >>> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >>> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >>> arm64: dts: tegra210: Add SDHCI tap and trim values >>> arm64: dts: tegra186: Add SDHCI tap and trim values >>> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >>> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >>> >>> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >>> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >>> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >>>
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 27/08/18 13:10, Thierry Reding wrote: > On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >> Hi all, >> >> This series implements support for faster signaling modes on Tegra >> SDHCI controllers. This series consist of several parts: changes >> requried for 1.8 V signaling and pad control, pad calibration, and >> tuning. Following earlies patch sets have been merged into this >> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >> padautocal procedure". Also the patches for enabling SDHCI tuning >> are added. >> >> Changelog: >> v2: >> - Fix grammar in PMC device tree bindings docs >> - Remove a stray line from tegra sdhci bindings >> - Cosmetic changes to PMC pinctrl driver >> - Fix a typo in "soc/tegra: pmc: Implement >>tegra_io_pad_is_powered()" commit message >> - Declare mask and value on the same line in >>tegra_io_pad_is_powered() >> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >>inside the if condition in tegra_sdhci_reset() >> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >> - Move sdhci_writel() out of the enable if-else body in >>tegra_sdhci_configure_cal_pad() >> - Add a delay before starting polling in >>tegra_sdhci_pad_autocalib() >> - Use usleep_range() in tegra_sdhci_set_tap() >> - Rename orig_enabled to status in >>tegra_sdhci_configure_card_clk() >> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >> >> v1: >> - Probe the regulator voltage capabilities to determine whether pinctrl >>is needed in tegra_sdhci_r eset >> - Don't remove tegra_sdhci_voltage_switch() >> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >> - Don't change start_signal_voltage_switch callback if pinctrl info >>invalid >> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >> - Add nvidia, prefix to pad autocal offset dt props in the example >> >> See the original patch sets for earlier changelogs. >> >> Aapo Vienamo (40): >> dt-bindings: Add Tegra PMC pad configuration bindings >> dt-bindings: mmc: tegra: Add pad voltage control properties >> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >> soc/tegra: pmc: Factor out DPD register bit calculation >> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >> soc/tegra: pmc: Use X macro to generate IO pad tables >> soc/tegra: pmc: Remove public pad voltage APIs >> soc/tegra: pmc: Implement pad configuration via pinctrl >> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >> tuning >> mmc: tegra: Reconfigure pad voltages during voltage switching >> mmc: tegra: Poll for calibration completion >> mmc: tegra: Set calibration pad voltage reference >> mmc: tegra: Power on the calibration pad >> mmc: tegra: Disable card clock during pad calibration >> mmc: tegra: Program pad autocal offsets from dt >> mmc: tegra: Perform pad calibration after voltage switch >> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >> mmc: tegra: Add a workaround for tap value change glitch >> mmc: tegra: Parse default trim and tap from dt >> mmc: tegra: Configure default tap values >> mmc: tegra: Configure default trim value on reset >> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >> mmc: sdhci: Add a quirk to disable card clock during tuning >> mmc: tegra: Enable workaround for tuning transfer mode bug >> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add SDHCI tap and trim values >> arm64: dts: tegra186: Add SDHCI tap and trim values >> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >> >> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- >> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - >>
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 27/08/18 13:10, Thierry Reding wrote: > On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >> Hi all, >> >> This series implements support for faster signaling modes on Tegra >> SDHCI controllers. This series consist of several parts: changes >> requried for 1.8 V signaling and pad control, pad calibration, and >> tuning. Following earlies patch sets have been merged into this >> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >> padautocal procedure". Also the patches for enabling SDHCI tuning >> are added. >> >> Changelog: >> v2: >> - Fix grammar in PMC device tree bindings docs >> - Remove a stray line from tegra sdhci bindings >> - Cosmetic changes to PMC pinctrl driver >> - Fix a typo in "soc/tegra: pmc: Implement >>tegra_io_pad_is_powered()" commit message >> - Declare mask and value on the same line in >>tegra_io_pad_is_powered() >> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >>inside the if condition in tegra_sdhci_reset() >> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >> - Move sdhci_writel() out of the enable if-else body in >>tegra_sdhci_configure_cal_pad() >> - Add a delay before starting polling in >>tegra_sdhci_pad_autocalib() >> - Use usleep_range() in tegra_sdhci_set_tap() >> - Rename orig_enabled to status in >>tegra_sdhci_configure_card_clk() >> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >> >> v1: >> - Probe the regulator voltage capabilities to determine whether pinctrl >>is needed in tegra_sdhci_r eset >> - Don't remove tegra_sdhci_voltage_switch() >> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >> - Don't change start_signal_voltage_switch callback if pinctrl info >>invalid >> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >> - Add nvidia, prefix to pad autocal offset dt props in the example >> >> See the original patch sets for earlier changelogs. >> >> Aapo Vienamo (40): >> dt-bindings: Add Tegra PMC pad configuration bindings >> dt-bindings: mmc: tegra: Add pad voltage control properties >> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >> soc/tegra: pmc: Factor out DPD register bit calculation >> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >> soc/tegra: pmc: Use X macro to generate IO pad tables >> soc/tegra: pmc: Remove public pad voltage APIs >> soc/tegra: pmc: Implement pad configuration via pinctrl >> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >> tuning >> mmc: tegra: Reconfigure pad voltages during voltage switching >> mmc: tegra: Poll for calibration completion >> mmc: tegra: Set calibration pad voltage reference >> mmc: tegra: Power on the calibration pad >> mmc: tegra: Disable card clock during pad calibration >> mmc: tegra: Program pad autocal offsets from dt >> mmc: tegra: Perform pad calibration after voltage switch >> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >> mmc: tegra: Add a workaround for tap value change glitch >> mmc: tegra: Parse default trim and tap from dt >> mmc: tegra: Configure default tap values >> mmc: tegra: Configure default trim value on reset >> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >> mmc: sdhci: Add a quirk to disable card clock during tuning >> mmc: tegra: Enable workaround for tuning transfer mode bug >> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add SDHCI tap and trim values >> arm64: dts: tegra186: Add SDHCI tap and trim values >> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >> >> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- >> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - >>
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. > > Changelog: > v2: > - Fix grammar in PMC device tree bindings docs > - Remove a stray line from tegra sdhci bindings > - Cosmetic changes to PMC pinctrl driver > - Fix a typo in "soc/tegra: pmc: Implement > tegra_io_pad_is_powered()" commit message > - Declare mask and value on the same line in > tegra_io_pad_is_powered() > - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to > inside the if condition in tegra_sdhci_reset() > - Use usleep_range() in tegra_sdhci_configure_cal_pad() > - Move sdhci_writel() out of the enable if-else body in > tegra_sdhci_configure_cal_pad() > - Add a delay before starting polling in > tegra_sdhci_pad_autocalib() > - Use usleep_range() in tegra_sdhci_set_tap() > - Rename orig_enabled to status in > tegra_sdhci_configure_card_clk() > - Fix if condition wrapping alignment in tegra_sdhci_set_tap() > > v1: > - Probe the regulator voltage capabilities to determine whether pinctrl > is needed in tegra_sdhci_r eset > - Don't remove tegra_sdhci_voltage_switch() > - Use dev_warn() in tegra_sdhci_init_pinctrl_info() > - Don't change start_signal_voltage_switch callback if pinctrl info > invalid > - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() > - Add nvidia, prefix to pad autocal offset dt props in the example > > See the original patch sets for earlier changelogs. > > Aapo Vienamo (40): > dt-bindings: Add Tegra PMC pad configuration bindings > dt-bindings: mmc: tegra: Add pad voltage control properties > dt-bindings: Add Tegra SDHCI pad pdpu offset bindings > dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values > soc/tegra: pmc: Fix pad voltage configuration for Tegra186 > soc/tegra: pmc: Factor out DPD register bit calculation > soc/tegra: pmc: Implement tegra_io_pad_is_powered() > soc/tegra: pmc: Use X macro to generate IO pad tables > soc/tegra: pmc: Remove public pad voltage APIs > soc/tegra: pmc: Implement pad configuration via pinctrl > mmc: sdhci: Add a quirk to skip clearing the transfer mode register on > tuning > mmc: tegra: Reconfigure pad voltages during voltage switching > mmc: tegra: Poll for calibration completion > mmc: tegra: Set calibration pad voltage reference > mmc: tegra: Power on the calibration pad > mmc: tegra: Disable card clock during pad calibration > mmc: tegra: Program pad autocal offsets from dt > mmc: tegra: Perform pad calibration after voltage switch > mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 > mmc: tegra: Add a workaround for tap value change glitch > mmc: tegra: Parse default trim and tap from dt > mmc: tegra: Configure default tap values > mmc: tegra: Configure default trim value on reset > mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 > mmc: sdhci: Add a quirk to disable card clock during tuning > mmc: tegra: Enable workaround for tuning transfer mode bug > mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra186 > arm64: dts: Add Tegra210 sdmmc pinctrl voltage states > arm64: dts: Add Tegra186 sdmmc pinctrl voltage states > arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V > arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply > arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 > arm64: dts: tegra186: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add SDHCI tap and trim values > arm64: dts: tegra186: Add SDHCI tap and trim values > arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 > arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 > > .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 > .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 > .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ > arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- > arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ > drivers/mmc/host/sdhci-tegra.c | 556 >
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. > > Changelog: > v2: > - Fix grammar in PMC device tree bindings docs > - Remove a stray line from tegra sdhci bindings > - Cosmetic changes to PMC pinctrl driver > - Fix a typo in "soc/tegra: pmc: Implement > tegra_io_pad_is_powered()" commit message > - Declare mask and value on the same line in > tegra_io_pad_is_powered() > - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to > inside the if condition in tegra_sdhci_reset() > - Use usleep_range() in tegra_sdhci_configure_cal_pad() > - Move sdhci_writel() out of the enable if-else body in > tegra_sdhci_configure_cal_pad() > - Add a delay before starting polling in > tegra_sdhci_pad_autocalib() > - Use usleep_range() in tegra_sdhci_set_tap() > - Rename orig_enabled to status in > tegra_sdhci_configure_card_clk() > - Fix if condition wrapping alignment in tegra_sdhci_set_tap() > > v1: > - Probe the regulator voltage capabilities to determine whether pinctrl > is needed in tegra_sdhci_r eset > - Don't remove tegra_sdhci_voltage_switch() > - Use dev_warn() in tegra_sdhci_init_pinctrl_info() > - Don't change start_signal_voltage_switch callback if pinctrl info > invalid > - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() > - Add nvidia, prefix to pad autocal offset dt props in the example > > See the original patch sets for earlier changelogs. > > Aapo Vienamo (40): > dt-bindings: Add Tegra PMC pad configuration bindings > dt-bindings: mmc: tegra: Add pad voltage control properties > dt-bindings: Add Tegra SDHCI pad pdpu offset bindings > dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values > soc/tegra: pmc: Fix pad voltage configuration for Tegra186 > soc/tegra: pmc: Factor out DPD register bit calculation > soc/tegra: pmc: Implement tegra_io_pad_is_powered() > soc/tegra: pmc: Use X macro to generate IO pad tables > soc/tegra: pmc: Remove public pad voltage APIs > soc/tegra: pmc: Implement pad configuration via pinctrl > mmc: sdhci: Add a quirk to skip clearing the transfer mode register on > tuning > mmc: tegra: Reconfigure pad voltages during voltage switching > mmc: tegra: Poll for calibration completion > mmc: tegra: Set calibration pad voltage reference > mmc: tegra: Power on the calibration pad > mmc: tegra: Disable card clock during pad calibration > mmc: tegra: Program pad autocal offsets from dt > mmc: tegra: Perform pad calibration after voltage switch > mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 > mmc: tegra: Add a workaround for tap value change glitch > mmc: tegra: Parse default trim and tap from dt > mmc: tegra: Configure default tap values > mmc: tegra: Configure default trim value on reset > mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 > mmc: sdhci: Add a quirk to disable card clock during tuning > mmc: tegra: Enable workaround for tuning transfer mode bug > mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra186 > arm64: dts: Add Tegra210 sdmmc pinctrl voltage states > arm64: dts: Add Tegra186 sdmmc pinctrl voltage states > arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V > arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply > arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 > arm64: dts: tegra186: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add SDHCI tap and trim values > arm64: dts: tegra186: Add SDHCI tap and trim values > arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 > arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 > > .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 > .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 > .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ > arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- > arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ > drivers/mmc/host/sdhci-tegra.c | 556 >
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 23 August 2018 at 10:47, Thierry Reding wrote: > On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >> Hi all, >> >> This series implements support for faster signaling modes on Tegra >> SDHCI controllers. This series consist of several parts: changes >> requried for 1.8 V signaling and pad control, pad calibration, and >> tuning. Following earlies patch sets have been merged into this >> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >> padautocal procedure". Also the patches for enabling SDHCI tuning >> are added. >> >> Changelog: >> v2: >> - Fix grammar in PMC device tree bindings docs >> - Remove a stray line from tegra sdhci bindings >> - Cosmetic changes to PMC pinctrl driver >> - Fix a typo in "soc/tegra: pmc: Implement >> tegra_io_pad_is_powered()" commit message >> - Declare mask and value on the same line in >> tegra_io_pad_is_powered() >> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >> inside the if condition in tegra_sdhci_reset() >> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >> - Move sdhci_writel() out of the enable if-else body in >> tegra_sdhci_configure_cal_pad() >> - Add a delay before starting polling in >> tegra_sdhci_pad_autocalib() >> - Use usleep_range() in tegra_sdhci_set_tap() >> - Rename orig_enabled to status in >> tegra_sdhci_configure_card_clk() >> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >> >> v1: >> - Probe the regulator voltage capabilities to determine whether pinctrl >> is needed in tegra_sdhci_r eset >> - Don't remove tegra_sdhci_voltage_switch() >> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >> - Don't change start_signal_voltage_switch callback if pinctrl info >> invalid >> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >> - Add nvidia, prefix to pad autocal offset dt props in the example >> >> See the original patch sets for earlier changelogs. >> >> Aapo Vienamo (40): >> dt-bindings: Add Tegra PMC pad configuration bindings >> dt-bindings: mmc: tegra: Add pad voltage control properties >> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >> soc/tegra: pmc: Factor out DPD register bit calculation >> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >> soc/tegra: pmc: Use X macro to generate IO pad tables >> soc/tegra: pmc: Remove public pad voltage APIs >> soc/tegra: pmc: Implement pad configuration via pinctrl >> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >> tuning >> mmc: tegra: Reconfigure pad voltages during voltage switching >> mmc: tegra: Poll for calibration completion >> mmc: tegra: Set calibration pad voltage reference >> mmc: tegra: Power on the calibration pad >> mmc: tegra: Disable card clock during pad calibration >> mmc: tegra: Program pad autocal offsets from dt >> mmc: tegra: Perform pad calibration after voltage switch >> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >> mmc: tegra: Add a workaround for tap value change glitch >> mmc: tegra: Parse default trim and tap from dt >> mmc: tegra: Configure default tap values >> mmc: tegra: Configure default trim value on reset >> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >> mmc: sdhci: Add a quirk to disable card clock during tuning >> mmc: tegra: Enable workaround for tuning transfer mode bug >> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add SDHCI tap and trim values >> arm64: dts: tegra186: Add SDHCI tap and trim values >> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >> >> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- >> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi |
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On 23 August 2018 at 10:47, Thierry Reding wrote: > On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: >> Hi all, >> >> This series implements support for faster signaling modes on Tegra >> SDHCI controllers. This series consist of several parts: changes >> requried for 1.8 V signaling and pad control, pad calibration, and >> tuning. Following earlies patch sets have been merged into this >> larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable >> 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the >> padautocal procedure". Also the patches for enabling SDHCI tuning >> are added. >> >> Changelog: >> v2: >> - Fix grammar in PMC device tree bindings docs >> - Remove a stray line from tegra sdhci bindings >> - Cosmetic changes to PMC pinctrl driver >> - Fix a typo in "soc/tegra: pmc: Implement >> tegra_io_pad_is_powered()" commit message >> - Declare mask and value on the same line in >> tegra_io_pad_is_powered() >> - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to >> inside the if condition in tegra_sdhci_reset() >> - Use usleep_range() in tegra_sdhci_configure_cal_pad() >> - Move sdhci_writel() out of the enable if-else body in >> tegra_sdhci_configure_cal_pad() >> - Add a delay before starting polling in >> tegra_sdhci_pad_autocalib() >> - Use usleep_range() in tegra_sdhci_set_tap() >> - Rename orig_enabled to status in >> tegra_sdhci_configure_card_clk() >> - Fix if condition wrapping alignment in tegra_sdhci_set_tap() >> >> v1: >> - Probe the regulator voltage capabilities to determine whether pinctrl >> is needed in tegra_sdhci_r eset >> - Don't remove tegra_sdhci_voltage_switch() >> - Use dev_warn() in tegra_sdhci_init_pinctrl_info() >> - Don't change start_signal_voltage_switch callback if pinctrl info >> invalid >> - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() >> - Add nvidia, prefix to pad autocal offset dt props in the example >> >> See the original patch sets for earlier changelogs. >> >> Aapo Vienamo (40): >> dt-bindings: Add Tegra PMC pad configuration bindings >> dt-bindings: mmc: tegra: Add pad voltage control properties >> dt-bindings: Add Tegra SDHCI pad pdpu offset bindings >> dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values >> soc/tegra: pmc: Fix pad voltage configuration for Tegra186 >> soc/tegra: pmc: Factor out DPD register bit calculation >> soc/tegra: pmc: Implement tegra_io_pad_is_powered() >> soc/tegra: pmc: Use X macro to generate IO pad tables >> soc/tegra: pmc: Remove public pad voltage APIs >> soc/tegra: pmc: Implement pad configuration via pinctrl >> mmc: sdhci: Add a quirk to skip clearing the transfer mode register on >> tuning >> mmc: tegra: Reconfigure pad voltages during voltage switching >> mmc: tegra: Poll for calibration completion >> mmc: tegra: Set calibration pad voltage reference >> mmc: tegra: Power on the calibration pad >> mmc: tegra: Disable card clock during pad calibration >> mmc: tegra: Program pad autocal offsets from dt >> mmc: tegra: Perform pad calibration after voltage switch >> mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 >> mmc: tegra: Add a workaround for tap value change glitch >> mmc: tegra: Parse default trim and tap from dt >> mmc: tegra: Configure default tap values >> mmc: tegra: Configure default trim value on reset >> mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 >> mmc: sdhci: Add a quirk to disable card clock during tuning >> mmc: tegra: Enable workaround for tuning transfer mode bug >> mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra210 >> mmc: tegra: Enable UHS and HS200 modes for Tegra186 >> arm64: dts: Add Tegra210 sdmmc pinctrl voltage states >> arm64: dts: Add Tegra186 sdmmc pinctrl voltage states >> arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V >> arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply >> arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 >> arm64: dts: tegra186: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add sdmmc pad auto calibration offsets >> arm64: dts: tegra210: Add SDHCI tap and trim values >> arm64: dts: tegra186: Add SDHCI tap and trim values >> arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 >> arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 >> >> .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 >> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 >> .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ >> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ >> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- >> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi |
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. > > Changelog: > v2: > - Fix grammar in PMC device tree bindings docs > - Remove a stray line from tegra sdhci bindings > - Cosmetic changes to PMC pinctrl driver > - Fix a typo in "soc/tegra: pmc: Implement > tegra_io_pad_is_powered()" commit message > - Declare mask and value on the same line in > tegra_io_pad_is_powered() > - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to > inside the if condition in tegra_sdhci_reset() > - Use usleep_range() in tegra_sdhci_configure_cal_pad() > - Move sdhci_writel() out of the enable if-else body in > tegra_sdhci_configure_cal_pad() > - Add a delay before starting polling in > tegra_sdhci_pad_autocalib() > - Use usleep_range() in tegra_sdhci_set_tap() > - Rename orig_enabled to status in > tegra_sdhci_configure_card_clk() > - Fix if condition wrapping alignment in tegra_sdhci_set_tap() > > v1: > - Probe the regulator voltage capabilities to determine whether pinctrl > is needed in tegra_sdhci_r eset > - Don't remove tegra_sdhci_voltage_switch() > - Use dev_warn() in tegra_sdhci_init_pinctrl_info() > - Don't change start_signal_voltage_switch callback if pinctrl info > invalid > - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() > - Add nvidia, prefix to pad autocal offset dt props in the example > > See the original patch sets for earlier changelogs. > > Aapo Vienamo (40): > dt-bindings: Add Tegra PMC pad configuration bindings > dt-bindings: mmc: tegra: Add pad voltage control properties > dt-bindings: Add Tegra SDHCI pad pdpu offset bindings > dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values > soc/tegra: pmc: Fix pad voltage configuration for Tegra186 > soc/tegra: pmc: Factor out DPD register bit calculation > soc/tegra: pmc: Implement tegra_io_pad_is_powered() > soc/tegra: pmc: Use X macro to generate IO pad tables > soc/tegra: pmc: Remove public pad voltage APIs > soc/tegra: pmc: Implement pad configuration via pinctrl > mmc: sdhci: Add a quirk to skip clearing the transfer mode register on > tuning > mmc: tegra: Reconfigure pad voltages during voltage switching > mmc: tegra: Poll for calibration completion > mmc: tegra: Set calibration pad voltage reference > mmc: tegra: Power on the calibration pad > mmc: tegra: Disable card clock during pad calibration > mmc: tegra: Program pad autocal offsets from dt > mmc: tegra: Perform pad calibration after voltage switch > mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 > mmc: tegra: Add a workaround for tap value change glitch > mmc: tegra: Parse default trim and tap from dt > mmc: tegra: Configure default tap values > mmc: tegra: Configure default trim value on reset > mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 > mmc: sdhci: Add a quirk to disable card clock during tuning > mmc: tegra: Enable workaround for tuning transfer mode bug > mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra186 > arm64: dts: Add Tegra210 sdmmc pinctrl voltage states > arm64: dts: Add Tegra186 sdmmc pinctrl voltage states > arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V > arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply > arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 > arm64: dts: tegra186: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add SDHCI tap and trim values > arm64: dts: tegra186: Add SDHCI tap and trim values > arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 > arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 > > .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 > .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 > .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ > arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- > arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ > drivers/mmc/host/sdhci-tegra.c | 556 >
Re: [PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
On Fri, Aug 10, 2018 at 09:08:02PM +0300, Aapo Vienamo wrote: > Hi all, > > This series implements support for faster signaling modes on Tegra > SDHCI controllers. This series consist of several parts: changes > requried for 1.8 V signaling and pad control, pad calibration, and > tuning. Following earlies patch sets have been merged into this > larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable > 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the > padautocal procedure". Also the patches for enabling SDHCI tuning > are added. > > Changelog: > v2: > - Fix grammar in PMC device tree bindings docs > - Remove a stray line from tegra sdhci bindings > - Cosmetic changes to PMC pinctrl driver > - Fix a typo in "soc/tegra: pmc: Implement > tegra_io_pad_is_powered()" commit message > - Declare mask and value on the same line in > tegra_io_pad_is_powered() > - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to > inside the if condition in tegra_sdhci_reset() > - Use usleep_range() in tegra_sdhci_configure_cal_pad() > - Move sdhci_writel() out of the enable if-else body in > tegra_sdhci_configure_cal_pad() > - Add a delay before starting polling in > tegra_sdhci_pad_autocalib() > - Use usleep_range() in tegra_sdhci_set_tap() > - Rename orig_enabled to status in > tegra_sdhci_configure_card_clk() > - Fix if condition wrapping alignment in tegra_sdhci_set_tap() > > v1: > - Probe the regulator voltage capabilities to determine whether pinctrl > is needed in tegra_sdhci_r eset > - Don't remove tegra_sdhci_voltage_switch() > - Use dev_warn() in tegra_sdhci_init_pinctrl_info() > - Don't change start_signal_voltage_switch callback if pinctrl info > invalid > - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() > - Add nvidia, prefix to pad autocal offset dt props in the example > > See the original patch sets for earlier changelogs. > > Aapo Vienamo (40): > dt-bindings: Add Tegra PMC pad configuration bindings > dt-bindings: mmc: tegra: Add pad voltage control properties > dt-bindings: Add Tegra SDHCI pad pdpu offset bindings > dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values > soc/tegra: pmc: Fix pad voltage configuration for Tegra186 > soc/tegra: pmc: Factor out DPD register bit calculation > soc/tegra: pmc: Implement tegra_io_pad_is_powered() > soc/tegra: pmc: Use X macro to generate IO pad tables > soc/tegra: pmc: Remove public pad voltage APIs > soc/tegra: pmc: Implement pad configuration via pinctrl > mmc: sdhci: Add a quirk to skip clearing the transfer mode register on > tuning > mmc: tegra: Reconfigure pad voltages during voltage switching > mmc: tegra: Poll for calibration completion > mmc: tegra: Set calibration pad voltage reference > mmc: tegra: Power on the calibration pad > mmc: tegra: Disable card clock during pad calibration > mmc: tegra: Program pad autocal offsets from dt > mmc: tegra: Perform pad calibration after voltage switch > mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 > mmc: tegra: Add a workaround for tap value change glitch > mmc: tegra: Parse default trim and tap from dt > mmc: tegra: Configure default tap values > mmc: tegra: Configure default trim value on reset > mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 > mmc: sdhci: Add a quirk to disable card clock during tuning > mmc: tegra: Enable workaround for tuning transfer mode bug > mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra210 > mmc: tegra: Enable UHS and HS200 modes for Tegra186 > arm64: dts: Add Tegra210 sdmmc pinctrl voltage states > arm64: dts: Add Tegra186 sdmmc pinctrl voltage states > arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V > arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply > arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 > arm64: dts: tegra186: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add sdmmc pad auto calibration offsets > arm64: dts: tegra210: Add SDHCI tap and trim values > arm64: dts: tegra186: Add SDHCI tap and trim values > arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 > arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 > > .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 > .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 > .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ > arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- > arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ > drivers/mmc/host/sdhci-tegra.c | 556 >
[PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
Hi all, This series implements support for faster signaling modes on Tegra SDHCI controllers. This series consist of several parts: changes requried for 1.8 V signaling and pad control, pad calibration, and tuning. Following earlies patch sets have been merged into this larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the padautocal procedure". Also the patches for enabling SDHCI tuning are added. Changelog: v2: - Fix grammar in PMC device tree bindings docs - Remove a stray line from tegra sdhci bindings - Cosmetic changes to PMC pinctrl driver - Fix a typo in "soc/tegra: pmc: Implement tegra_io_pad_is_powered()" commit message - Declare mask and value on the same line in tegra_io_pad_is_powered() - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to inside the if condition in tegra_sdhci_reset() - Use usleep_range() in tegra_sdhci_configure_cal_pad() - Move sdhci_writel() out of the enable if-else body in tegra_sdhci_configure_cal_pad() - Add a delay before starting polling in tegra_sdhci_pad_autocalib() - Use usleep_range() in tegra_sdhci_set_tap() - Rename orig_enabled to status in tegra_sdhci_configure_card_clk() - Fix if condition wrapping alignment in tegra_sdhci_set_tap() v1: - Probe the regulator voltage capabilities to determine whether pinctrl is needed in tegra_sdhci_r eset - Don't remove tegra_sdhci_voltage_switch() - Use dev_warn() in tegra_sdhci_init_pinctrl_info() - Don't change start_signal_voltage_switch callback if pinctrl info invalid - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() - Add nvidia, prefix to pad autocal offset dt props in the example See the original patch sets for earlier changelogs. Aapo Vienamo (40): dt-bindings: Add Tegra PMC pad configuration bindings dt-bindings: mmc: tegra: Add pad voltage control properties dt-bindings: Add Tegra SDHCI pad pdpu offset bindings dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Implement tegra_io_pad_is_powered() soc/tegra: pmc: Use X macro to generate IO pad tables soc/tegra: pmc: Remove public pad voltage APIs soc/tegra: pmc: Implement pad configuration via pinctrl mmc: sdhci: Add a quirk to skip clearing the transfer mode register on tuning mmc: tegra: Reconfigure pad voltages during voltage switching mmc: tegra: Poll for calibration completion mmc: tegra: Set calibration pad voltage reference mmc: tegra: Power on the calibration pad mmc: tegra: Disable card clock during pad calibration mmc: tegra: Program pad autocal offsets from dt mmc: tegra: Perform pad calibration after voltage switch mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 mmc: tegra: Add a workaround for tap value change glitch mmc: tegra: Parse default trim and tap from dt mmc: tegra: Configure default tap values mmc: tegra: Configure default trim value on reset mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 mmc: sdhci: Add a quirk to disable card clock during tuning mmc: tegra: Enable workaround for tuning transfer mode bug mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 mmc: tegra: Enable UHS and HS200 modes for Tegra210 mmc: tegra: Enable UHS and HS200 modes for Tegra186 arm64: dts: Add Tegra210 sdmmc pinctrl voltage states arm64: dts: Add Tegra186 sdmmc pinctrl voltage states arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 arm64: dts: tegra186: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add SDHCI tap and trim values arm64: dts: tegra186: Add SDHCI tap and trim values arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ drivers/mmc/host/sdhci-tegra.c | 556 +++-- drivers/mmc/host/sdhci.c | 21 + drivers/mmc/host/sdhci.h | 4 + drivers/soc/tegra/pmc.c| 511
[PATCH v2 00/40] Tegra SDHCI add support for HS200 and UHS signaling
Hi all, This series implements support for faster signaling modes on Tegra SDHCI controllers. This series consist of several parts: changes requried for 1.8 V signaling and pad control, pad calibration, and tuning. Following earlies patch sets have been merged into this larger set: "Tegra PMC pinctrl pad configuration", "Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186", "Tegra SDHCI update the padautocal procedure". Also the patches for enabling SDHCI tuning are added. Changelog: v2: - Fix grammar in PMC device tree bindings docs - Remove a stray line from tegra sdhci bindings - Cosmetic changes to PMC pinctrl driver - Fix a typo in "soc/tegra: pmc: Implement tegra_io_pad_is_powered()" commit message - Declare mask and value on the same line in tegra_io_pad_is_powered() - Move the call to tegra_sdhci_is_pad_and_regulator_valid() to inside the if condition in tegra_sdhci_reset() - Use usleep_range() in tegra_sdhci_configure_cal_pad() - Move sdhci_writel() out of the enable if-else body in tegra_sdhci_configure_cal_pad() - Add a delay before starting polling in tegra_sdhci_pad_autocalib() - Use usleep_range() in tegra_sdhci_set_tap() - Rename orig_enabled to status in tegra_sdhci_configure_card_clk() - Fix if condition wrapping alignment in tegra_sdhci_set_tap() v1: - Probe the regulator voltage capabilities to determine whether pinctrl is needed in tegra_sdhci_r eset - Don't remove tegra_sdhci_voltage_switch() - Use dev_warn() in tegra_sdhci_init_pinctrl_info() - Don't change start_signal_voltage_switch callback if pinctrl info invalid - Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() - Add nvidia, prefix to pad autocal offset dt props in the example See the original patch sets for earlier changelogs. Aapo Vienamo (40): dt-bindings: Add Tegra PMC pad configuration bindings dt-bindings: mmc: tegra: Add pad voltage control properties dt-bindings: Add Tegra SDHCI pad pdpu offset bindings dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Implement tegra_io_pad_is_powered() soc/tegra: pmc: Use X macro to generate IO pad tables soc/tegra: pmc: Remove public pad voltage APIs soc/tegra: pmc: Implement pad configuration via pinctrl mmc: sdhci: Add a quirk to skip clearing the transfer mode register on tuning mmc: tegra: Reconfigure pad voltages during voltage switching mmc: tegra: Poll for calibration completion mmc: tegra: Set calibration pad voltage reference mmc: tegra: Power on the calibration pad mmc: tegra: Disable card clock during pad calibration mmc: tegra: Program pad autocal offsets from dt mmc: tegra: Perform pad calibration after voltage switch mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 mmc: tegra: Add a workaround for tap value change glitch mmc: tegra: Parse default trim and tap from dt mmc: tegra: Configure default tap values mmc: tegra: Configure default trim value on reset mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 mmc: sdhci: Add a quirk to disable card clock during tuning mmc: tegra: Enable workaround for tuning transfer mode bug mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210 mmc: tegra: Enable UHS and HS200 modes for Tegra210 mmc: tegra: Enable UHS and HS200 modes for Tegra186 arm64: dts: Add Tegra210 sdmmc pinctrl voltage states arm64: dts: Add Tegra186 sdmmc pinctrl voltage states arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 arm64: dts: tegra186: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add SDHCI tap and trim values arm64: dts: tegra186: Add SDHCI tap and trim values arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4 .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 93 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 68 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 74 +++ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra210.dtsi | 55 ++ drivers/mmc/host/sdhci-tegra.c | 556 +++-- drivers/mmc/host/sdhci.c | 21 + drivers/mmc/host/sdhci.h | 4 + drivers/soc/tegra/pmc.c| 511
