Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-24 Thread Rich Felker 
On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote:
> On 23/05/16 22:13, Rich Felker wrote:
> > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> >> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> >>> Signed-off-by: Rich Felker 
> >>> ---
> >>>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> >>> ++
> >>>  1 file changed, 28 insertions(+)
> >>>  create mode 100644 
> >>> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>>
> >>> diff --git 
> >>> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> >>> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> new file mode 100644
> >>> index 000..dc9fde8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> @@ -0,0 +1,28 @@
> >>> +J-Core Advanced Interrupt Controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible : Should be "jcore,aic1" for the (obsolete) 
> >>> first-generation aic
> >>> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" 
> >>> for
> >>> +  the "aic2" core with 64 interrupts.
> >>> +
> >>> +- interrupt-controller : Identifies the node as an interrupt controller
> >>> +
> >>> +- #interrupt-cells : Specifies the number of cells needed to encode an
> >>> +  interrupt source. The value shall be 1.
> >>
> >> No level/edge support? Need 2 cells if so.
> > 
> > No, all the logic is in hardware. From the software side you just need
> > handle_simple_irq or equivalent.
> 
> Not even an EOI?

What I mean is that there is no ack/eoi interface. While I haven't
worked directly on the relevant vhdl, my understanding is that the aic
clears the pending status of an interrupt atomically with acceptance
of the interrupt by the cpu.

Do you have any more specific questions I can try to answer?

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-24 Thread Rich Felker 
On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote:
> On 23/05/16 22:13, Rich Felker wrote:
> > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> >> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> >>> Signed-off-by: Rich Felker 
> >>> ---
> >>>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> >>> ++
> >>>  1 file changed, 28 insertions(+)
> >>>  create mode 100644 
> >>> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>>
> >>> diff --git 
> >>> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> >>> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> new file mode 100644
> >>> index 000..dc9fde8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> @@ -0,0 +1,28 @@
> >>> +J-Core Advanced Interrupt Controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible : Should be "jcore,aic1" for the (obsolete) 
> >>> first-generation aic
> >>> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" 
> >>> for
> >>> +  the "aic2" core with 64 interrupts.
> >>> +
> >>> +- interrupt-controller : Identifies the node as an interrupt controller
> >>> +
> >>> +- #interrupt-cells : Specifies the number of cells needed to encode an
> >>> +  interrupt source. The value shall be 1.
> >>
> >> No level/edge support? Need 2 cells if so.
> > 
> > No, all the logic is in hardware. From the software side you just need
> > handle_simple_irq or equivalent.
> 
> Not even an EOI?

What I mean is that there is no ack/eoi interface. While I haven't
worked directly on the relevant vhdl, my understanding is that the aic
clears the pending status of an interrupt atomically with acceptance
of the interrupt by the cpu.

Do you have any more specific questions I can try to answer?

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-24 Thread Marc Zyngier 
On 23/05/16 22:13, Rich Felker wrote:
> On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
>> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
>>> Signed-off-by: Rich Felker 
>>> ---
>>>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
>>> ++
>>>  1 file changed, 28 insertions(+)
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
>>> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> new file mode 100644
>>> index 000..dc9fde8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> @@ -0,0 +1,28 @@
>>> +J-Core Advanced Interrupt Controller
>>> +
>>> +Required properties:
>>> +
>>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation 
>>> aic
>>> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
>>> +  the "aic2" core with 64 interrupts.
>>> +
>>> +- interrupt-controller : Identifies the node as an interrupt controller
>>> +
>>> +- #interrupt-cells : Specifies the number of cells needed to encode an
>>> +  interrupt source. The value shall be 1.
>>
>> No level/edge support? Need 2 cells if so.
> 
> No, all the logic is in hardware. From the software side you just need
> handle_simple_irq or equivalent.

Not even an EOI?

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-24 Thread Marc Zyngier 
On 23/05/16 22:13, Rich Felker wrote:
> On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
>> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
>>> Signed-off-by: Rich Felker 
>>> ---
>>>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
>>> ++
>>>  1 file changed, 28 insertions(+)
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
>>> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> new file mode 100644
>>> index 000..dc9fde8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> @@ -0,0 +1,28 @@
>>> +J-Core Advanced Interrupt Controller
>>> +
>>> +Required properties:
>>> +
>>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation 
>>> aic
>>> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
>>> +  the "aic2" core with 64 interrupts.
>>> +
>>> +- interrupt-controller : Identifies the node as an interrupt controller
>>> +
>>> +- #interrupt-cells : Specifies the number of cells needed to encode an
>>> +  interrupt source. The value shall be 1.
>>
>> No level/edge support? Need 2 cells if so.
> 
> No, all the logic is in hardware. From the software side you just need
> handle_simple_irq or equivalent.

Not even an EOI?

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-23 Thread Rich Felker 
On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> > Signed-off-by: Rich Felker 
> > ---
> >  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> > ++
> >  1 file changed, 28 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> > b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 000..dc9fde8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,28 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation 
> > aic
> > +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > +  the "aic2" core with 64 interrupts.
> > +
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > +  interrupt source. The value shall be 1.
> 
> No level/edge support? Need 2 cells if so.

No, all the logic is in hardware. From the software side you just need
handle_simple_irq or equivalent.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-23 Thread Rich Felker 
On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> > Signed-off-by: Rich Felker 
> > ---
> >  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> > ++
> >  1 file changed, 28 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> > b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 000..dc9fde8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,28 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation 
> > aic
> > +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > +  the "aic2" core with 64 interrupts.
> > +
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > +  interrupt source. The value shall be 1.
> 
> No level/edge support? Need 2 cells if so.

No, all the logic is in hardware. From the software side you just need
handle_simple_irq or equivalent.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-23 Thread Rob Herring 
On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> Signed-off-by: Rich Felker 
> ---
>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> ++
>  1 file changed, 28 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> 
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 000..dc9fde8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,28 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> +  the "aic2" core with 64 interrupts.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.

No level/edge support? Need 2 cells if so.

> +
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> +  configuration, to be scaled by the cpu number.
> +
> +
> +Example:
> +
> +aic: interrupt-controller {
> + compatible = "jcore,aic2";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> -- 
> 2.8.1
> 
>

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-23 Thread Rob Herring 
On Fri, May 20, 2016 at 02:53:04AM +, Rich Felker wrote:
> Signed-off-by: Rich Felker 
> ---
>  .../bindings/interrupt-controller/jcore,aic.txt| 28 
> ++
>  1 file changed, 28 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> 
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 000..dc9fde8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,28 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> +  the "aic2" core with 64 interrupts.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.

No level/edge support? Need 2 cells if so.

> +
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> +  configuration, to be scaled by the cpu number.
> +
> +
> +Example:
> +
> +aic: interrupt-controller {
> + compatible = "jcore,aic2";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> -- 
> 2.8.1
> 
>

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-21 Thread Rich Felker 
On Sat, May 21, 2016 at 08:07:54PM +0200, Geert Uytterhoeven wrote:
> On Sat, May 21, 2016 at 12:34 AM, Rich Felker  wrote:
> > On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> >> > +Additional properties required for aic1:
> >> > +
> >> > +- reg : Memory region for configuration.
> >> > +
> >> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> >> > +  configuration, to be scaled by the cpu number.
> >>
> >> Does cpu-offset apply to aic1 only?
> >
> > The current kernel driver doesn't have any reason to _need_ cpu-offset
> > for aic2, but since there are registers there that a driver (even a
> > non-Linux one) may want to use, I think it makes sense that it should
> > be present in the bindings.
> 
> Hence the "for aic1" should be dropped?

Yes, I've fixed that locally. Moved reg to required and cpu-offset
to optional but needed for smp.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-21 Thread Rich Felker 
On Sat, May 21, 2016 at 08:07:54PM +0200, Geert Uytterhoeven wrote:
> On Sat, May 21, 2016 at 12:34 AM, Rich Felker  wrote:
> > On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> >> > +Additional properties required for aic1:
> >> > +
> >> > +- reg : Memory region for configuration.
> >> > +
> >> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> >> > +  configuration, to be scaled by the cpu number.
> >>
> >> Does cpu-offset apply to aic1 only?
> >
> > The current kernel driver doesn't have any reason to _need_ cpu-offset
> > for aic2, but since there are registers there that a driver (even a
> > non-Linux one) may want to use, I think it makes sense that it should
> > be present in the bindings.
> 
> Hence the "for aic1" should be dropped?

Yes, I've fixed that locally. Moved reg to required and cpu-offset
to optional but needed for smp.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-21 Thread Geert Uytterhoeven 
On Sat, May 21, 2016 at 12:34 AM, Rich Felker  wrote:
> On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
>> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
>> > +Additional properties required for aic1:
>> > +
>> > +- reg : Memory region for configuration.
>> > +
>> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
>> > +  configuration, to be scaled by the cpu number.
>>
>> Does cpu-offset apply to aic1 only?
>
> The current kernel driver doesn't have any reason to _need_ cpu-offset
> for aic2, but since there are registers there that a driver (even a
> non-Linux one) may want to use, I think it makes sense that it should
> be present in the bindings.

Hence the "for aic1" should be dropped?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-21 Thread Geert Uytterhoeven 
On Sat, May 21, 2016 at 12:34 AM, Rich Felker  wrote:
> On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
>> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
>> > +Additional properties required for aic1:
>> > +
>> > +- reg : Memory region for configuration.
>> > +
>> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
>> > +  configuration, to be scaled by the cpu number.
>>
>> Does cpu-offset apply to aic1 only?
>
> The current kernel driver doesn't have any reason to _need_ cpu-offset
> for aic2, but since there are registers there that a driver (even a
> non-Linux one) may want to use, I think it makes sense that it should
> be present in the bindings.

Hence the "for aic1" should be dropped?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-20 Thread Rich Felker 
On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> > +Additional properties required for aic1:
> > +
> > +- reg : Memory region for configuration.
> > +
> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> > +  configuration, to be scaled by the cpu number.
> 
> Does cpu-offset apply to aic1 only?

The current kernel driver doesn't have any reason to _need_ cpu-offset
for aic2, but since there are registers there that a driver (even a
non-Linux one) may want to use, I think it makes sense that it should
be present in the bindings.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-20 Thread Rich Felker 
On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> > +Additional properties required for aic1:
> > +
> > +- reg : Memory region for configuration.
> > +
> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> > +  configuration, to be scaled by the cpu number.
> 
> Does cpu-offset apply to aic1 only?

The current kernel driver doesn't have any reason to _need_ cpu-offset
for aic2, but since there are registers there that a driver (even a
non-Linux one) may want to use, I think it makes sense that it should
be present in the bindings.

Rich

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-20 Thread Geert Uytterhoeven 
On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> +  configuration, to be scaled by the cpu number.

Does cpu-offset apply to aic1 only?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-20 Thread Geert Uytterhoeven 
On Fri, May 20, 2016 at 4:53 AM, Rich Felker  wrote:
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> +  configuration, to be scaled by the cpu number.

Does cpu-offset apply to aic1 only?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-19 Thread Rich Felker 
Signed-off-by: Rich Felker 
---
 .../bindings/interrupt-controller/jcore,aic.txt| 28 ++
 1 file changed, 28 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 000..dc9fde8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,28 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
+  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+  the "aic2" core with 64 interrupts.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+Additional properties required for aic1:
+
+- reg : Memory region for configuration.
+
+- cpu-offset : For SMP, the offset to the per-cpu memory region for
+  configuration, to be scaled by the cpu number.
+
+
+Example:
+
+aic: interrupt-controller {
+   compatible = "jcore,aic2";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
-- 
2.8.1

[PATCH v2 03/12] of: add J-Core interrupt controller bindings

2016-05-19 Thread Rich Felker 
Signed-off-by: Rich Felker 
---
 .../bindings/interrupt-controller/jcore,aic.txt| 28 ++
 1 file changed, 28 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 000..dc9fde8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,28 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
+  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+  the "aic2" core with 64 interrupts.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+Additional properties required for aic1:
+
+- reg : Memory region for configuration.
+
+- cpu-offset : For SMP, the offset to the per-cpu memory region for
+  configuration, to be scaled by the cpu number.
+
+
+Example:
+
+aic: interrupt-controller {
+   compatible = "jcore,aic2";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
-- 
2.8.1