Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
On Tue, 2016-04-19 at 10:33 +0200, Alessio Igor Bogani wrote: > Hi Scott, > > Thanks for reviewing it! > > On 19 April 2016 at 06:26, Scott Woodwrote: > > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: > > > + pci0: pcie@f1008000 { > > > + reg = <0xf1008000 0x1000>; > > > + ranges = <0x0200 0x0 0x8000 0x8000 0x0 > > > 0x5000 > > > + 0x0100 0x0 0x 0xf000 0x0 > > > 0x0080>; > [...] > > > + > > > + pci1: pcie@f1009000 { > > > + compatible = "fsl,mpc8641-pcie"; > > > + device_type = "pci"; > > > + #size-cells = <2>; > > > + #address-cells = <3>; > > > + reg = <0xf1009000 0x1000>; > > > + bus-range = <0 0xff>; > > > > Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have > > pci1? > > You are right. The MPC8641 processor offers two pci so > mpc8641si-post.dtsi should be the right place where to define both. > What about the boards which don't use the pci1? Will 'status = > "disabled"' be enough? Yes. -Scott
Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
On Tue, 2016-04-19 at 10:33 +0200, Alessio Igor Bogani wrote: > Hi Scott, > > Thanks for reviewing it! > > On 19 April 2016 at 06:26, Scott Wood wrote: > > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: > > > + pci0: pcie@f1008000 { > > > + reg = <0xf1008000 0x1000>; > > > + ranges = <0x0200 0x0 0x8000 0x8000 0x0 > > > 0x5000 > > > + 0x0100 0x0 0x 0xf000 0x0 > > > 0x0080>; > [...] > > > + > > > + pci1: pcie@f1009000 { > > > + compatible = "fsl,mpc8641-pcie"; > > > + device_type = "pci"; > > > + #size-cells = <2>; > > > + #address-cells = <3>; > > > + reg = <0xf1009000 0x1000>; > > > + bus-range = <0 0xff>; > > > > Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have > > pci1? > > You are right. The MPC8641 processor offers two pci so > mpc8641si-post.dtsi should be the right place where to define both. > What about the boards which don't use the pci1? Will 'status = > "disabled"' be enough? Yes. -Scott
Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
Hi Scott, Thanks for reviewing it! On 19 April 2016 at 06:26, Scott Woodwrote: > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: >> + pci0: pcie@f1008000 { >> + reg = <0xf1008000 0x1000>; >> + ranges = <0x0200 0x0 0x8000 0x8000 0x0 >> 0x5000 >> + 0x0100 0x0 0x 0xf000 0x0 >> 0x0080>; [...] >> + >> + pci1: pcie@f1009000 { >> + compatible = "fsl,mpc8641-pcie"; >> + device_type = "pci"; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + reg = <0xf1009000 0x1000>; >> + bus-range = <0 0xff>; > > Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have > pci1? You are right. The MPC8641 processor offers two pci so mpc8641si-post.dtsi should be the right place where to define both. What about the boards which don't use the pci1? Will 'status = "disabled"' be enough? >> +asm(".globl _zimage_start\n\ >> + _zimage_start:\n\ >> + mfmsr 10\n\ >> + rlwinm 10,10,0,~(1<<15)/* Clear MSR_EE */\n\ >> + sync\n\ >> + mtmsr 10\n\ >> + isync\n\ >> + b _zimage_start_lib\n\ >> +"); > > Please put this in an asm file. Ok. > Is U-Boot really not clearing MSR[EE]? How old is this U-Boot? [...] >> + defined(TARGET_83xx) || defined(TARGET_MVME7100) >> unsigned long bi_immr_base; /* base of IMMR register [...] > TARGET_86xx would match the U-Boot definition better. [...] >> + _set_L2CR(_get_L2CR() | L2CR_L2E); [...] > U-Boot doesn't enable L2 cache? In fact it isn't U-Boot but MotLoad which it doesn't clear MSR[EE] and disable L2 cache just before pass control to operating system. It seems to be partially compatible with older version of U-Boot (boot/mvme7100.c) but I wasn't able to use an uImage to boot so I have switched to the dtbImage target. Thanks! Ciao, Alessio
Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
Hi Scott, Thanks for reviewing it! On 19 April 2016 at 06:26, Scott Wood wrote: > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: >> + pci0: pcie@f1008000 { >> + reg = <0xf1008000 0x1000>; >> + ranges = <0x0200 0x0 0x8000 0x8000 0x0 >> 0x5000 >> + 0x0100 0x0 0x 0xf000 0x0 >> 0x0080>; [...] >> + >> + pci1: pcie@f1009000 { >> + compatible = "fsl,mpc8641-pcie"; >> + device_type = "pci"; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + reg = <0xf1009000 0x1000>; >> + bus-range = <0 0xff>; > > Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have > pci1? You are right. The MPC8641 processor offers two pci so mpc8641si-post.dtsi should be the right place where to define both. What about the boards which don't use the pci1? Will 'status = "disabled"' be enough? >> +asm(".globl _zimage_start\n\ >> + _zimage_start:\n\ >> + mfmsr 10\n\ >> + rlwinm 10,10,0,~(1<<15)/* Clear MSR_EE */\n\ >> + sync\n\ >> + mtmsr 10\n\ >> + isync\n\ >> + b _zimage_start_lib\n\ >> +"); > > Please put this in an asm file. Ok. > Is U-Boot really not clearing MSR[EE]? How old is this U-Boot? [...] >> + defined(TARGET_83xx) || defined(TARGET_MVME7100) >> unsigned long bi_immr_base; /* base of IMMR register [...] > TARGET_86xx would match the U-Boot definition better. [...] >> + _set_L2CR(_get_L2CR() | L2CR_L2E); [...] > U-Boot doesn't enable L2 cache? In fact it isn't U-Boot but MotLoad which it doesn't clear MSR[EE] and disable L2 cache just before pass control to operating system. It seems to be partially compatible with older version of U-Boot (boot/mvme7100.c) but I wasn't able to use an uImage to boot so I have switched to the dtbImage target. Thanks! Ciao, Alessio
Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: > + pci0: pcie@f1008000 { > + reg = <0xf1008000 0x1000>; > + ranges = <0x0200 0x0 0x8000 0x8000 0x0 > 0x5000 > + 0x0100 0x0 0x 0xf000 0x0 > 0x0080>; > + pcie@0 { > + ranges = <0x0200 0x0 0x8000 > + 0x0200 0x0 0x8000 > + 0x0 0x5000 > + > + 0x0100 0x0 0x > + 0x0100 0x0 0x > + 0x0 0x0080>; > + }; > + }; > + > + pci1: pcie@f1009000 { > + compatible = "fsl,mpc8641-pcie"; > + device_type = "pci"; > + #size-cells = <2>; > + #address-cells = <3>; > + reg = <0xf1009000 0x1000>; > + bus-range = <0 0xff>; Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have pci1? > +asm(".globl _zimage_start\n\ > + _zimage_start:\n\ > + mfmsr 10\n\ > + rlwinm 10,10,0,~(1<<15)/* Clear MSR_EE */\n\ > + sync\n\ > + mtmsr 10\n\ > + isync\n\ > + b _zimage_start_lib\n\ > +"); Please put this in an asm file. Is U-Boot really not clearing MSR[EE]? How old is this U-Boot? > diff --git a/arch/powerpc/boot/ppcboot.h b/arch/powerpc/boot/ppcboot.h > index 6ae6f90..7b758be 100644 > --- a/arch/powerpc/boot/ppcboot.h > +++ b/arch/powerpc/boot/ppcboot.h > @@ -43,7 +43,7 @@ typedef struct bd_info { > unsigned long bi_sramstart; /* start of SRAM memory > */ > unsigned long bi_sramsize;/* size of SRAM > memory */ > #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\ > - defined(TARGET_83xx) > + defined(TARGET_83xx) || defined(TARGET_MVME7100) > unsigned long bi_immr_base; /* base of IMMR register > */ > #endif TARGET_86xx would match the U-Boot definition better. > +/* > + * Called very early, device-tree isn't unflattened > + */ > +static int __init mvme7100_probe(void) > +{ > + unsigned long root = of_get_flat_dt_root(); > + > + if (!of_flat_dt_is_compatible(root, "artesyn,MVME7100")) > + return 0; > + > + _set_L2CR(_get_L2CR() | L2CR_L2E); > + return 1; > +} U-Boot doesn't enable L2 cache? -Scott
Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: > + pci0: pcie@f1008000 { > + reg = <0xf1008000 0x1000>; > + ranges = <0x0200 0x0 0x8000 0x8000 0x0 > 0x5000 > + 0x0100 0x0 0x 0xf000 0x0 > 0x0080>; > + pcie@0 { > + ranges = <0x0200 0x0 0x8000 > + 0x0200 0x0 0x8000 > + 0x0 0x5000 > + > + 0x0100 0x0 0x > + 0x0100 0x0 0x > + 0x0 0x0080>; > + }; > + }; > + > + pci1: pcie@f1009000 { > + compatible = "fsl,mpc8641-pcie"; > + device_type = "pci"; > + #size-cells = <2>; > + #address-cells = <3>; > + reg = <0xf1009000 0x1000>; > + bus-range = <0 0xff>; Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have pci1? > +asm(".globl _zimage_start\n\ > + _zimage_start:\n\ > + mfmsr 10\n\ > + rlwinm 10,10,0,~(1<<15)/* Clear MSR_EE */\n\ > + sync\n\ > + mtmsr 10\n\ > + isync\n\ > + b _zimage_start_lib\n\ > +"); Please put this in an asm file. Is U-Boot really not clearing MSR[EE]? How old is this U-Boot? > diff --git a/arch/powerpc/boot/ppcboot.h b/arch/powerpc/boot/ppcboot.h > index 6ae6f90..7b758be 100644 > --- a/arch/powerpc/boot/ppcboot.h > +++ b/arch/powerpc/boot/ppcboot.h > @@ -43,7 +43,7 @@ typedef struct bd_info { > unsigned long bi_sramstart; /* start of SRAM memory > */ > unsigned long bi_sramsize;/* size of SRAM > memory */ > #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\ > - defined(TARGET_83xx) > + defined(TARGET_83xx) || defined(TARGET_MVME7100) > unsigned long bi_immr_base; /* base of IMMR register > */ > #endif TARGET_86xx would match the U-Boot definition better. > +/* > + * Called very early, device-tree isn't unflattened > + */ > +static int __init mvme7100_probe(void) > +{ > + unsigned long root = of_get_flat_dt_root(); > + > + if (!of_flat_dt_is_compatible(root, "artesyn,MVME7100")) > + return 0; > + > + _set_L2CR(_get_L2CR() | L2CR_L2E); > + return 1; > +} U-Boot doesn't enable L2 cache? -Scott
[PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
Add support for the Artesyn MVME7100 Single Board Computer. The MVME7100 is a 6U form factor VME64 computer with: - A two e600 cores Freescale MPC8641D CPU - 2 GB of DDR2 onboard memory - Four Gigabit Ethernets - Five 16550 compatible UARTs - One USB 2.0 port - Two PCI/PCI eXpress Mezzanine Card (PMC/XMC) Slots - A DS1375 Real Time Clock (RTC) - 512 KB of Non-Volatile Memory (NVRAM) - Two 64 KB EEPROMs - 128 MB NOR and 4/8 GB NAND Flash This patch is based on linux-4.6-rc4 and has been only boot tested. Signed-off-by: Alessio Igor Bogani--- v1 -> v2 Fix BCSR handling Add missing @interrupt-cells in the device tree to avoid 'of_irq_parse_pci() failed with rc=-22' Reduce from 3 to 2 the PCI windows to avoid 'Ran out of outbound PCI ATMUs for IO resource' This patch requires https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141813.html to be built and https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141785.html to work correctly. Limitations: This patch covers only models 171 and 173 No plans to support CPLD timers Know issues: All four PHYs work in polling mode Configuration is missing for: PCI IDSEL and PCI Interrupt definition Support is missing for: Cache and memory controllers (which are very similar to the 85xx ones but right now I don't know if we can re-use their support) Watchdog, USB, NVRAM, NOR, NAND, EEPROMs, VME, PMC/XMC and RTC arch/powerpc/boot/Makefile | 4 + arch/powerpc/boot/dts/fsl/mvme7100.dts | 206 +++ arch/powerpc/boot/mvme7100.c | 70 + arch/powerpc/boot/ppcboot.h | 2 +- arch/powerpc/boot/wrapper| 4 + arch/powerpc/configs/mpc86xx_basic_defconfig | 1 + arch/powerpc/platforms/86xx/Kconfig | 7 +- arch/powerpc/platforms/86xx/Makefile | 1 + arch/powerpc/platforms/86xx/mvme7100.c | 124 9 files changed, 417 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/mvme7100.dts create mode 100644 arch/powerpc/boot/mvme7100.c create mode 100644 arch/powerpc/platforms/86xx/mvme7100.c diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 8fe78a3..2c75fdb 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -113,6 +113,7 @@ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S +src-plat-$(CONFIG_MVME7100) += mvme7100.c src-wlib := $(sort $(src-wlib-y)) src-plat := $(sort $(src-plat-y)) @@ -296,6 +297,9 @@ image-$(CONFIG_TQM8560) += cuImage.tqm8560 image-$(CONFIG_SBC8548)+= cuImage.sbc8548 image-$(CONFIG_KSI8560)+= cuImage.ksi8560 +# Board ports in arch/powerpc/platform/86xx/Kconfig +image-$(CONFIG_MVME7100)+= dtbImage.mvme7100 + # Board ports in arch/powerpc/platform/embedded6xx/Kconfig image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2)+= cuImage.mpc7448hpc2 diff --git a/arch/powerpc/boot/dts/fsl/mvme7100.dts b/arch/powerpc/boot/dts/fsl/mvme7100.dts new file mode 100644 index 000..2fdb912 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/mvme7100.dts @@ -0,0 +1,206 @@ +/* + * Device tree source for the Emerson/Artesyn MVME7100 + * + * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. + * + * Author: Alessio Igor Bogani + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/include/ "mpc8641si-pre.dtsi" + +/ { + model = "MVME7100"; + compatible = "artesyn,MVME7100"; + + aliases { + pci1 = + }; + + memory { + device_type = "memory"; + reg = <0x 0x8000>; + }; + + soc: soc@f100 { + ranges = <0x 0xf100 0x0010>; + + i2c@3000 { + hwmon@4c { + compatible = "dallas,max6649"; + reg = <0x4c>; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + + enet0: ethernet@24000 { + phy-handle = <>; + phy-connection-type = "rgmii-id"; + }; + + mdio@24520 { + phy0: ethernet-phy@1 { +
[PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100
Add support for the Artesyn MVME7100 Single Board Computer. The MVME7100 is a 6U form factor VME64 computer with: - A two e600 cores Freescale MPC8641D CPU - 2 GB of DDR2 onboard memory - Four Gigabit Ethernets - Five 16550 compatible UARTs - One USB 2.0 port - Two PCI/PCI eXpress Mezzanine Card (PMC/XMC) Slots - A DS1375 Real Time Clock (RTC) - 512 KB of Non-Volatile Memory (NVRAM) - Two 64 KB EEPROMs - 128 MB NOR and 4/8 GB NAND Flash This patch is based on linux-4.6-rc4 and has been only boot tested. Signed-off-by: Alessio Igor Bogani --- v1 -> v2 Fix BCSR handling Add missing @interrupt-cells in the device tree to avoid 'of_irq_parse_pci() failed with rc=-22' Reduce from 3 to 2 the PCI windows to avoid 'Ran out of outbound PCI ATMUs for IO resource' This patch requires https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141813.html to be built and https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-April/141785.html to work correctly. Limitations: This patch covers only models 171 and 173 No plans to support CPLD timers Know issues: All four PHYs work in polling mode Configuration is missing for: PCI IDSEL and PCI Interrupt definition Support is missing for: Cache and memory controllers (which are very similar to the 85xx ones but right now I don't know if we can re-use their support) Watchdog, USB, NVRAM, NOR, NAND, EEPROMs, VME, PMC/XMC and RTC arch/powerpc/boot/Makefile | 4 + arch/powerpc/boot/dts/fsl/mvme7100.dts | 206 +++ arch/powerpc/boot/mvme7100.c | 70 + arch/powerpc/boot/ppcboot.h | 2 +- arch/powerpc/boot/wrapper| 4 + arch/powerpc/configs/mpc86xx_basic_defconfig | 1 + arch/powerpc/platforms/86xx/Kconfig | 7 +- arch/powerpc/platforms/86xx/Makefile | 1 + arch/powerpc/platforms/86xx/mvme7100.c | 124 9 files changed, 417 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/boot/dts/fsl/mvme7100.dts create mode 100644 arch/powerpc/boot/mvme7100.c create mode 100644 arch/powerpc/platforms/86xx/mvme7100.c diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 8fe78a3..2c75fdb 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -113,6 +113,7 @@ src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S +src-plat-$(CONFIG_MVME7100) += mvme7100.c src-wlib := $(sort $(src-wlib-y)) src-plat := $(sort $(src-plat-y)) @@ -296,6 +297,9 @@ image-$(CONFIG_TQM8560) += cuImage.tqm8560 image-$(CONFIG_SBC8548)+= cuImage.sbc8548 image-$(CONFIG_KSI8560)+= cuImage.ksi8560 +# Board ports in arch/powerpc/platform/86xx/Kconfig +image-$(CONFIG_MVME7100)+= dtbImage.mvme7100 + # Board ports in arch/powerpc/platform/embedded6xx/Kconfig image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2)+= cuImage.mpc7448hpc2 diff --git a/arch/powerpc/boot/dts/fsl/mvme7100.dts b/arch/powerpc/boot/dts/fsl/mvme7100.dts new file mode 100644 index 000..2fdb912 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/mvme7100.dts @@ -0,0 +1,206 @@ +/* + * Device tree source for the Emerson/Artesyn MVME7100 + * + * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. + * + * Author: Alessio Igor Bogani + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/include/ "mpc8641si-pre.dtsi" + +/ { + model = "MVME7100"; + compatible = "artesyn,MVME7100"; + + aliases { + pci1 = + }; + + memory { + device_type = "memory"; + reg = <0x 0x8000>; + }; + + soc: soc@f100 { + ranges = <0x 0xf100 0x0010>; + + i2c@3000 { + hwmon@4c { + compatible = "dallas,max6649"; + reg = <0x4c>; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + + enet0: ethernet@24000 { + phy-handle = <>; + phy-connection-type = "rgmii-id"; + }; + + mdio@24520 { + phy0: ethernet-phy@1 { + reg = <1>; +