Re: [PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Ralph Sennhauser]

On Fri, 24 Mar 2017 10:18:29 -0500
Rob Herring  wrote:

> On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote:
> > From: Andrew Lunn 
> > 
> > Armada 370/XP devices can 'blink' gpio lines with a configurable on
> > and off period. This can be modelled as a PWM.
> > 
> > However, there are only two sets of PWM configuration registers for
> > all the gpio lines. This driver simply allows a single gpio line per
> > gpio chip of 32 lines to be used as a PWM. Attempts to use more
> > return EBUSY.
> > 
> > Due to the interleaving of registers it is not simple to separate
> > the PWM driver from the gpio driver. Thus the gpio driver has been
> > extended with a PWM driver.
> > 
> > Signed-off-by: Andrew Lunn 
> > URL: https://patchwork.ozlabs.org/patch/427287/
> > URL: https://patchwork.ozlabs.org/patch/427295/
> > [Ralph Sennhauser:
> >   * port forward
> >   * merge pwm portion into gpio-mvebu.c
> >   * merge documentation patch
> >   * update MAINTAINERS]
> > Signed-off-by: Ralph Sennhauser 
> > ---
> >  .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
> >  MAINTAINERS|   2 +
> >  drivers/gpio/gpio-mvebu.c  | 291
> > +++-- 3 files changed, 307 insertions(+), 17
> > deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index
> > a6f3bec..86932e3 100644 ---
> > a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -38,6
> > +38,23 @@ Required properties:
> >  - #gpio-cells: Should be two. The first cell is the pin number. The
> >second cell is reserved for flags, unused at the moment.
> >  
> > +Optional properties:
> > +
> > +In order to use the gpio lines in PWM mode, some additional
> > optional +properties are required. Only Armada 370 and XP support
> > these properties. +
> > +- reg: an additional register set is needed, for the GPIO Blink
> > +  Counter on/off registers.
> > +
> > +- reg-names: Must contain an entry "pwm" corresponding to the
> > +  additional register range needed for pwm operation.
> > +
> > +- #pwm-cells: Should be two. The first cell is the pin number.
> > The  
> 
> s/pin number/gpio line/ ?

Better indeed.

> 
> > +  second cell is reserved for flags and should be set to 0, so it
> > has a
> > +  known value. It then becomes possible to use it in the future.
> > +
> > +- clocks: Must be a phandle to the clock for the gpio controller.
> > +
> >  Example:
> >  
> > gpio0: gpio@d0018100 {
> > @@ -51,3 +68,17 @@ Example:
> > #interrupt-cells = <2>;
> > interrupts = <16>, <17>, <18>, <19>;
> > };
> > +
> > +   gpio1: gpio@18140 {
> > +   compatible = "marvell,orion-gpio";  
> 
> If only 370 and XP support this, I'd expect a compatible string for
> one of them here.

Commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on
Armada XP") changes it from "marvell,armadaxp-gpio". The commit message
says for 3.8 basically leaving it open for a "fix" later.

Adding Thomas Petazzoni as the author.

Thomas, would you happen to know if this is still how it's supposed to
be for now?

Thanks
Ralph


> 
> > +   reg = <0x18140 0x40>, <0x181c8 0x08>;
> > +   reg-names = "gpio", "pwm";
> > +   ngpios = <17>;
> > +   gpio-controller;
> > +   #gpio-cells = <2>;
> > +   #pwm-cells = <2>;
> > +   interrupt-controller;
> > +   #interrupt-cells = <2>;
> > +   interrupts = <87>, <88>, <89>;
> > +   clocks = < 0>;
> > +   };  

Re: [PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Ralph Sennhauser]

On Fri, 24 Mar 2017 10:18:29 -0500
Rob Herring  wrote:

> On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote:
> > From: Andrew Lunn 
> > 
> > Armada 370/XP devices can 'blink' gpio lines with a configurable on
> > and off period. This can be modelled as a PWM.
> > 
> > However, there are only two sets of PWM configuration registers for
> > all the gpio lines. This driver simply allows a single gpio line per
> > gpio chip of 32 lines to be used as a PWM. Attempts to use more
> > return EBUSY.
> > 
> > Due to the interleaving of registers it is not simple to separate
> > the PWM driver from the gpio driver. Thus the gpio driver has been
> > extended with a PWM driver.
> > 
> > Signed-off-by: Andrew Lunn 
> > URL: https://patchwork.ozlabs.org/patch/427287/
> > URL: https://patchwork.ozlabs.org/patch/427295/
> > [Ralph Sennhauser:
> >   * port forward
> >   * merge pwm portion into gpio-mvebu.c
> >   * merge documentation patch
> >   * update MAINTAINERS]
> > Signed-off-by: Ralph Sennhauser 
> > ---
> >  .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
> >  MAINTAINERS|   2 +
> >  drivers/gpio/gpio-mvebu.c  | 291
> > +++-- 3 files changed, 307 insertions(+), 17
> > deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt index
> > a6f3bec..86932e3 100644 ---
> > a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +++
> > b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -38,6
> > +38,23 @@ Required properties:
> >  - #gpio-cells: Should be two. The first cell is the pin number. The
> >second cell is reserved for flags, unused at the moment.
> >  
> > +Optional properties:
> > +
> > +In order to use the gpio lines in PWM mode, some additional
> > optional +properties are required. Only Armada 370 and XP support
> > these properties. +
> > +- reg: an additional register set is needed, for the GPIO Blink
> > +  Counter on/off registers.
> > +
> > +- reg-names: Must contain an entry "pwm" corresponding to the
> > +  additional register range needed for pwm operation.
> > +
> > +- #pwm-cells: Should be two. The first cell is the pin number.
> > The  
> 
> s/pin number/gpio line/ ?

Better indeed.

> 
> > +  second cell is reserved for flags and should be set to 0, so it
> > has a
> > +  known value. It then becomes possible to use it in the future.
> > +
> > +- clocks: Must be a phandle to the clock for the gpio controller.
> > +
> >  Example:
> >  
> > gpio0: gpio@d0018100 {
> > @@ -51,3 +68,17 @@ Example:
> > #interrupt-cells = <2>;
> > interrupts = <16>, <17>, <18>, <19>;
> > };
> > +
> > +   gpio1: gpio@18140 {
> > +   compatible = "marvell,orion-gpio";  
> 
> If only 370 and XP support this, I'd expect a compatible string for
> one of them here.

Commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on
Armada XP") changes it from "marvell,armadaxp-gpio". The commit message
says for 3.8 basically leaving it open for a "fix" later.

Adding Thomas Petazzoni as the author.

Thomas, would you happen to know if this is still how it's supposed to
be for now?

Thanks
Ralph


> 
> > +   reg = <0x18140 0x40>, <0x181c8 0x08>;
> > +   reg-names = "gpio", "pwm";
> > +   ngpios = <17>;
> > +   gpio-controller;
> > +   #gpio-cells = <2>;
> > +   #pwm-cells = <2>;
> > +   interrupt-controller;
> > +   #interrupt-cells = <2>;
> > +   interrupts = <87>, <88>, <89>;
> > +   clocks = < 0>;
> > +   };  

Re: [PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Rob Herring]

On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote:
> From: Andrew Lunn 
> 
> Armada 370/XP devices can 'blink' gpio lines with a configurable on
> and off period. This can be modelled as a PWM.
> 
> However, there are only two sets of PWM configuration registers for
> all the gpio lines. This driver simply allows a single gpio line per
> gpio chip of 32 lines to be used as a PWM. Attempts to use more return
> EBUSY.
> 
> Due to the interleaving of registers it is not simple to separate the
> PWM driver from the gpio driver. Thus the gpio driver has been
> extended with a PWM driver.
> 
> Signed-off-by: Andrew Lunn 
> URL: https://patchwork.ozlabs.org/patch/427287/
> URL: https://patchwork.ozlabs.org/patch/427295/
> [Ralph Sennhauser:
>   * port forward
>   * merge pwm portion into gpio-mvebu.c
>   * merge documentation patch
>   * update MAINTAINERS]
> Signed-off-by: Ralph Sennhauser 
> ---
>  .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
>  MAINTAINERS|   2 +
>  drivers/gpio/gpio-mvebu.c  | 291 
> +++--
>  3 files changed, 307 insertions(+), 17 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
> b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> index a6f3bec..86932e3 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> @@ -38,6 +38,23 @@ Required properties:
>  - #gpio-cells: Should be two. The first cell is the pin number. The
>second cell is reserved for flags, unused at the moment.
>  
> +Optional properties:
> +
> +In order to use the gpio lines in PWM mode, some additional optional
> +properties are required. Only Armada 370 and XP support these properties.
> +
> +- reg: an additional register set is needed, for the GPIO Blink
> +  Counter on/off registers.
> +
> +- reg-names: Must contain an entry "pwm" corresponding to the
> +  additional register range needed for pwm operation.
> +
> +- #pwm-cells: Should be two. The first cell is the pin number. The

s/pin number/gpio line/ ?

> +  second cell is reserved for flags and should be set to 0, so it has a
> +  known value. It then becomes possible to use it in the future.
> +
> +- clocks: Must be a phandle to the clock for the gpio controller.
> +
>  Example:
>  
>   gpio0: gpio@d0018100 {
> @@ -51,3 +68,17 @@ Example:
>   #interrupt-cells = <2>;
>   interrupts = <16>, <17>, <18>, <19>;
>   };
> +
> + gpio1: gpio@18140 {
> + compatible = "marvell,orion-gpio";

If only 370 and XP support this, I'd expect a compatible string for one 
of them here.

> + reg = <0x18140 0x40>, <0x181c8 0x08>;
> + reg-names = "gpio", "pwm";
> + ngpios = <17>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #pwm-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <87>, <88>, <89>;
> + clocks = < 0>;
> + };

Re: [PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Rob Herring]

On Sat, Mar 18, 2017 at 04:43:01PM +0100, Ralph Sennhauser wrote:
> From: Andrew Lunn 
> 
> Armada 370/XP devices can 'blink' gpio lines with a configurable on
> and off period. This can be modelled as a PWM.
> 
> However, there are only two sets of PWM configuration registers for
> all the gpio lines. This driver simply allows a single gpio line per
> gpio chip of 32 lines to be used as a PWM. Attempts to use more return
> EBUSY.
> 
> Due to the interleaving of registers it is not simple to separate the
> PWM driver from the gpio driver. Thus the gpio driver has been
> extended with a PWM driver.
> 
> Signed-off-by: Andrew Lunn 
> URL: https://patchwork.ozlabs.org/patch/427287/
> URL: https://patchwork.ozlabs.org/patch/427295/
> [Ralph Sennhauser:
>   * port forward
>   * merge pwm portion into gpio-mvebu.c
>   * merge documentation patch
>   * update MAINTAINERS]
> Signed-off-by: Ralph Sennhauser 
> ---
>  .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
>  MAINTAINERS|   2 +
>  drivers/gpio/gpio-mvebu.c  | 291 
> +++--
>  3 files changed, 307 insertions(+), 17 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
> b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> index a6f3bec..86932e3 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
> @@ -38,6 +38,23 @@ Required properties:
>  - #gpio-cells: Should be two. The first cell is the pin number. The
>second cell is reserved for flags, unused at the moment.
>  
> +Optional properties:
> +
> +In order to use the gpio lines in PWM mode, some additional optional
> +properties are required. Only Armada 370 and XP support these properties.
> +
> +- reg: an additional register set is needed, for the GPIO Blink
> +  Counter on/off registers.
> +
> +- reg-names: Must contain an entry "pwm" corresponding to the
> +  additional register range needed for pwm operation.
> +
> +- #pwm-cells: Should be two. The first cell is the pin number. The

s/pin number/gpio line/ ?

> +  second cell is reserved for flags and should be set to 0, so it has a
> +  known value. It then becomes possible to use it in the future.
> +
> +- clocks: Must be a phandle to the clock for the gpio controller.
> +
>  Example:
>  
>   gpio0: gpio@d0018100 {
> @@ -51,3 +68,17 @@ Example:
>   #interrupt-cells = <2>;
>   interrupts = <16>, <17>, <18>, <19>;
>   };
> +
> + gpio1: gpio@18140 {
> + compatible = "marvell,orion-gpio";

If only 370 and XP support this, I'd expect a compatible string for one 
of them here.

> + reg = <0x18140 0x40>, <0x181c8 0x08>;
> + reg-names = "gpio", "pwm";
> + ngpios = <17>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #pwm-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <87>, <88>, <89>;
> + clocks = < 0>;
> + };

[PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Ralph Sennhauser]

From: Andrew Lunn 

Armada 370/XP devices can 'blink' gpio lines with a configurable on
and off period. This can be modelled as a PWM.

However, there are only two sets of PWM configuration registers for
all the gpio lines. This driver simply allows a single gpio line per
gpio chip of 32 lines to be used as a PWM. Attempts to use more return
EBUSY.

Due to the interleaving of registers it is not simple to separate the
PWM driver from the gpio driver. Thus the gpio driver has been
extended with a PWM driver.

Signed-off-by: Andrew Lunn 
URL: https://patchwork.ozlabs.org/patch/427287/
URL: https://patchwork.ozlabs.org/patch/427295/
[Ralph Sennhauser:
  * port forward
  * merge pwm portion into gpio-mvebu.c
  * merge documentation patch
  * update MAINTAINERS]
Signed-off-by: Ralph Sennhauser 
---
 .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
 MAINTAINERS|   2 +
 drivers/gpio/gpio-mvebu.c  | 291 +++--
 3 files changed, 307 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index a6f3bec..86932e3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -38,6 +38,23 @@ Required properties:
 - #gpio-cells: Should be two. The first cell is the pin number. The
   second cell is reserved for flags, unused at the moment.
 
+Optional properties:
+
+In order to use the gpio lines in PWM mode, some additional optional
+properties are required. Only Armada 370 and XP support these properties.
+
+- reg: an additional register set is needed, for the GPIO Blink
+  Counter on/off registers.
+
+- reg-names: Must contain an entry "pwm" corresponding to the
+  additional register range needed for pwm operation.
+
+- #pwm-cells: Should be two. The first cell is the pin number. The
+  second cell is reserved for flags and should be set to 0, so it has a
+  known value. It then becomes possible to use it in the future.
+
+- clocks: Must be a phandle to the clock for the gpio controller.
+
 Example:
 
gpio0: gpio@d0018100 {
@@ -51,3 +68,17 @@ Example:
#interrupt-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
+
+   gpio1: gpio@18140 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x18140 0x40>, <0x181c8 0x08>;
+   reg-names = "gpio", "pwm";
+   ngpios = <17>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   #pwm-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <87>, <88>, <89>;
+   clocks = < 0>;
+   };
diff --git a/MAINTAINERS b/MAINTAINERS
index 40ac605..efe3a22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10266,6 +10266,8 @@ F:  include/linux/pwm.h
 F: drivers/pwm/
 F: drivers/video/backlight/pwm_bl.c
 F: include/linux/pwm_backlight.h
+F: drivers/gpio/gpio-mvebu.c
+F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
 
 PXA2xx/PXA3xx SUPPORT
 M: Daniel Mack 
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index fae4db6..ee49589 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,22 +42,34 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
+#include "gpiolib.h"
+
 /*
  * GPIO unit register offsets.
  */
-#define GPIO_OUT_OFF   0x
-#define GPIO_IO_CONF_OFF   0x0004
-#define GPIO_BLINK_EN_OFF  0x0008
-#define GPIO_IN_POL_OFF0x000c
-#define GPIO_DATA_IN_OFF   0x0010
-#define GPIO_EDGE_CAUSE_OFF0x0014
-#define GPIO_EDGE_MASK_OFF 0x0018
-#define GPIO_LEVEL_MASK_OFF0x001c
+#define GPIO_OUT_OFF   0x
+#define GPIO_IO_CONF_OFF   0x0004
+#define GPIO_BLINK_EN_OFF  0x0008
+#define GPIO_IN_POL_OFF0x000c
+#define GPIO_DATA_IN_OFF   0x0010
+#define GPIO_EDGE_CAUSE_OFF0x0014
+#define GPIO_EDGE_MASK_OFF 0x0018
+#define GPIO_LEVEL_MASK_OFF0x001c
+#define GPIO_BLINK_CNT_SELECT_OFF  0x0020
+
+/*
+ * PWM register offsets.
+ */
+#define PWM_BLINK_ON_DURATION_OFF  0x0
+#define PWM_BLINK_OFF_DURATION_OFF 0x4
+
 
 /* The MV78200 has per-CPU registers for edge mask and level mask */
 #define GPIO_EDGE_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x30 : 0x18)
@@ -78,6 +90,21 @@
 
 #define MVEBU_MAX_GPIO_PER_BANK32
 
+struct mvebu_pwm {
+   void __iomem*membase;
+   unsigned longclk_rate;
+   bool 

[PATCH v2 1/4] gpio: mvebu: Add limited PWM support

[Ralph Sennhauser]

From: Andrew Lunn 

Armada 370/XP devices can 'blink' gpio lines with a configurable on
and off period. This can be modelled as a PWM.

However, there are only two sets of PWM configuration registers for
all the gpio lines. This driver simply allows a single gpio line per
gpio chip of 32 lines to be used as a PWM. Attempts to use more return
EBUSY.

Due to the interleaving of registers it is not simple to separate the
PWM driver from the gpio driver. Thus the gpio driver has been
extended with a PWM driver.

Signed-off-by: Andrew Lunn 
URL: https://patchwork.ozlabs.org/patch/427287/
URL: https://patchwork.ozlabs.org/patch/427295/
[Ralph Sennhauser:
  * port forward
  * merge pwm portion into gpio-mvebu.c
  * merge documentation patch
  * update MAINTAINERS]
Signed-off-by: Ralph Sennhauser 
---
 .../devicetree/bindings/gpio/gpio-mvebu.txt|  31 +++
 MAINTAINERS|   2 +
 drivers/gpio/gpio-mvebu.c  | 291 +++--
 3 files changed, 307 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt 
b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index a6f3bec..86932e3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -38,6 +38,23 @@ Required properties:
 - #gpio-cells: Should be two. The first cell is the pin number. The
   second cell is reserved for flags, unused at the moment.
 
+Optional properties:
+
+In order to use the gpio lines in PWM mode, some additional optional
+properties are required. Only Armada 370 and XP support these properties.
+
+- reg: an additional register set is needed, for the GPIO Blink
+  Counter on/off registers.
+
+- reg-names: Must contain an entry "pwm" corresponding to the
+  additional register range needed for pwm operation.
+
+- #pwm-cells: Should be two. The first cell is the pin number. The
+  second cell is reserved for flags and should be set to 0, so it has a
+  known value. It then becomes possible to use it in the future.
+
+- clocks: Must be a phandle to the clock for the gpio controller.
+
 Example:
 
gpio0: gpio@d0018100 {
@@ -51,3 +68,17 @@ Example:
#interrupt-cells = <2>;
interrupts = <16>, <17>, <18>, <19>;
};
+
+   gpio1: gpio@18140 {
+   compatible = "marvell,orion-gpio";
+   reg = <0x18140 0x40>, <0x181c8 0x08>;
+   reg-names = "gpio", "pwm";
+   ngpios = <17>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   #pwm-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <87>, <88>, <89>;
+   clocks = < 0>;
+   };
diff --git a/MAINTAINERS b/MAINTAINERS
index 40ac605..efe3a22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10266,6 +10266,8 @@ F:  include/linux/pwm.h
 F: drivers/pwm/
 F: drivers/video/backlight/pwm_bl.c
 F: include/linux/pwm_backlight.h
+F: drivers/gpio/gpio-mvebu.c
+F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
 
 PXA2xx/PXA3xx SUPPORT
 M: Daniel Mack 
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index fae4db6..ee49589 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -42,22 +42,34 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
+#include "gpiolib.h"
+
 /*
  * GPIO unit register offsets.
  */
-#define GPIO_OUT_OFF   0x
-#define GPIO_IO_CONF_OFF   0x0004
-#define GPIO_BLINK_EN_OFF  0x0008
-#define GPIO_IN_POL_OFF0x000c
-#define GPIO_DATA_IN_OFF   0x0010
-#define GPIO_EDGE_CAUSE_OFF0x0014
-#define GPIO_EDGE_MASK_OFF 0x0018
-#define GPIO_LEVEL_MASK_OFF0x001c
+#define GPIO_OUT_OFF   0x
+#define GPIO_IO_CONF_OFF   0x0004
+#define GPIO_BLINK_EN_OFF  0x0008
+#define GPIO_IN_POL_OFF0x000c
+#define GPIO_DATA_IN_OFF   0x0010
+#define GPIO_EDGE_CAUSE_OFF0x0014
+#define GPIO_EDGE_MASK_OFF 0x0018
+#define GPIO_LEVEL_MASK_OFF0x001c
+#define GPIO_BLINK_CNT_SELECT_OFF  0x0020
+
+/*
+ * PWM register offsets.
+ */
+#define PWM_BLINK_ON_DURATION_OFF  0x0
+#define PWM_BLINK_OFF_DURATION_OFF 0x4
+
 
 /* The MV78200 has per-CPU registers for edge mask and level mask */
 #define GPIO_EDGE_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x30 : 0x18)
@@ -78,6 +90,21 @@
 
 #define MVEBU_MAX_GPIO_PER_BANK32
 
+struct mvebu_pwm {
+   void __iomem*membase;
+   unsigned longclk_rate;
+   bool used;
+   unsigned int pin;
+   struct