Re: [PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
Hi Robin,
Thank you for your comments.
The old binding txt is not so up to date.
The question is now what do we add or not..
On 2/4/21 12:35 PM, Robin Murphy wrote:
> On 2021-02-03 16:52, Johan Jonker wrote:
>> In the past Rockchip dwc3 usb nodes were manually checked.
>> With the conversion of snps,dwc3.yaml as common document
>> we now can convert rockchip,dwc3.txt to yaml as well.
>> Remove node wrapper.
>>
>> Added properties for rk3399 are:
>> power-domains
>> resets
>> reset-names
>>
>> Signed-off-by: Johan Jonker
>> ---
>> .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ---
>> .../devicetree/bindings/usb/rockchip,dwc3.yaml | 103
>> +
>> 2 files changed, 103 insertions(+), 56 deletions(-)
>> delete mode 100644
>> Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> create mode 100644
>> Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> deleted file mode 100644
>> index 945204932..0
>> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
>> +++ /dev/null
>> @@ -1,56 +0,0 @@
>> -Rockchip SuperSpeed DWC3 USB SoC controller
>> -
>> -Required properties:
>> -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
>> -- clocks: A list of phandle + clock-specifier pairs for the
>> - clocks listed in clock-names
>> -- clock-names: Should contain the following:
>> - "ref_clk" Controller reference clk, have to be 24 MHz
>> - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
>> - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
>> - operation and >= 30MHz for HS operation
>> - "grf_clk" Controller grf clk
>> -
>> -Required child node:
>> -A child node must exist to represent the core DWC3 IP block. The name of
>> -the node is not important. The content of the node is defined in
>> dwc3.txt.
>> -
>> -Phy documentation is provided in the following places:
>> -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml -
>> USB2.0 PHY
>> -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt -
>> Type-C PHY
>> -
>> -Example device nodes:
>> -
>> - usbdrd3_0: usb@fe80 {
>> - compatible = "rockchip,rk3399-dwc3";
>> - clocks = < SCLK_USB3OTG0_REF>, < SCLK_USB3OTG0_SUSPEND>,
>> - < ACLK_USB3OTG0>, < ACLK_USB3_GRF>;
>> - clock-names = "ref_clk", "suspend_clk",
>> - "bus_clk", "grf_clk";
>> - #address-cells = <2>;
>> - #size-cells = <2>;
>> - ranges;
>> - usbdrd_dwc3_0: dwc3@fe80 {
>> - compatible = "snps,dwc3";
>> - reg = <0x0 0xfe80 0x0 0x10>;
>> - interrupts = ;
>> - dr_mode = "otg";
>> - };
>> - };
>> -
>> - usbdrd3_1: usb@fe90 {
>> - compatible = "rockchip,rk3399-dwc3";
>> - clocks = < SCLK_USB3OTG1_REF>, < SCLK_USB3OTG1_SUSPEND>,
>> - < ACLK_USB3OTG1>, < ACLK_USB3_GRF>;
>> - clock-names = "ref_clk", "suspend_clk",
>> - "bus_clk", "grf_clk";
>> - #address-cells = <2>;
>> - #size-cells = <2>;
>> - ranges;
>> - usbdrd_dwc3_1: dwc3@fe90 {
>> - compatible = "snps,dwc3";
>> - reg = <0x0 0xfe90 0x0 0x10>;
>> - interrupts = ;
>> - dr_mode = "otg";
>> - };
>> - };
>> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>> new file mode 100644
>> index 0..fdf9497bc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>> @@ -0,0 +1,103 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Rockchip SuperSpeed DWC3 USB SoC controller
>> +
>> +maintainers:
>> + - Heiko Stuebner
>> +
>> +description:
>> + The common content of the node is defined in snps,dwc3.yaml.
>> +
>> + Phy documentation is provided in the following places.
>> +
>> + USB2.0 PHY
>> + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
>> +
>> + Type-C PHY
>> + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>> +
>> +allOf:
>> + - $ref: snps,dwc3.yaml#
Could Rob advise here? Is this OK or not?
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - rockchip,rk3399-dwc3
>> + - const: snps,dwc3
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description:
>> + Controller reference clock, must to be 24 MHz
>> + - description:
>> + Controller suspend clock, must to be 24 MHz or 32 KHz
>> +
Re: [PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
On Wed, 03 Feb 2021 17:52:27 +0100, Johan Jonker wrote: > In the past Rockchip dwc3 usb nodes were manually checked. > With the conversion of snps,dwc3.yaml as common document > we now can convert rockchip,dwc3.txt to yaml as well. > Remove node wrapper. > > Added properties for rk3399 are: > power-domains > resets > reset-names > > Signed-off-by: Johan Jonker > --- > .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 --- > .../devicetree/bindings/usb/rockchip,dwc3.yaml | 103 > + > 2 files changed, 103 insertions(+), 56 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml:13:7: [warning] wrong indentation: expected 2 but found 6 (indentation) dtschema/dtc warnings/errors: Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml' xargs: dt-doc-validate: exited with status 255; aborting make[1]: *** Deleting file 'Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml' Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml' make[1]: *** [scripts/Makefile.lib:344: Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml] Error 255 make[1]: *** Waiting for unfinished jobs make[1]: *** Deleting file 'Documentation/devicetree/bindings/usb/intel,keembay-dwc3.example.dt.yaml' Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml' make[1]: *** [scripts/Makefile.lib:344: Documentation/devicetree/bindings/usb/intel,keembay-dwc3.example.dt.yaml] Error 255 make[1]: *** Deleting file 'Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.example.dt.yaml' Unknown file referenced: [Errno 2] No such file or directory: '/usr/local/lib/python3.8/dist-packages/dtschema/schemas/usb/snps,dwc3.yaml' make[1]: *** [scripts/Makefile.lib:344: Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.example.dt.yaml] Error 255 make: *** [Makefile:1370: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1435466 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Re: [PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
On 2021-02-03 16:52, Johan Jonker wrote:
In the past Rockchip dwc3 usb nodes were manually checked.
With the conversion of snps,dwc3.yaml as common document
we now can convert rockchip,dwc3.txt to yaml as well.
Remove node wrapper.
Added properties for rk3399 are:
power-domains
resets
reset-names
Signed-off-by: Johan Jonker
---
.../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ---
.../devicetree/bindings/usb/rockchip,dwc3.yaml | 103 +
2 files changed, 103 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
deleted file mode 100644
index 945204932..0
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks: A list of phandle + clock-specifier pairs for the
- clocks listed in clock-names
-- clock-names: Should contain the following:
- "ref_clk" Controller reference clk, have to be 24 MHz
- "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
- "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
- operation and >= 30MHz for HS operation
- "grf_clk" Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
-Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
-
-Example device nodes:
-
- usbdrd3_0: usb@fe80 {
- compatible = "rockchip,rk3399-dwc3";
- clocks = < SCLK_USB3OTG0_REF>, < SCLK_USB3OTG0_SUSPEND>,
-< ACLK_USB3OTG0>, < ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- usbdrd_dwc3_0: dwc3@fe80 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe80 0x0 0x10>;
- interrupts = ;
- dr_mode = "otg";
- };
- };
-
- usbdrd3_1: usb@fe90 {
- compatible = "rockchip,rk3399-dwc3";
- clocks = < SCLK_USB3OTG1_REF>, < SCLK_USB3OTG1_SUSPEND>,
-< ACLK_USB3OTG1>, < ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- usbdrd_dwc3_1: dwc3@fe90 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe90 0x0 0x10>;
- interrupts = ;
- dr_mode = "otg";
- };
- };
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
new file mode 100644
index 0..fdf9497bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+ - Heiko Stuebner
+
+description:
+ The common content of the node is defined in snps,dwc3.yaml.
+
+ Phy documentation is provided in the following places.
+
+ USB2.0 PHY
+ Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+
+ Type-C PHY
+ Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+
+allOf:
+ - $ref: snps,dwc3.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ - rockchip,rk3399-dwc3
+ - const: snps,dwc3
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description:
+ Controller reference clock, must to be 24 MHz
+ - description:
+ Controller suspend clock, must to be 24 MHz or 32 KHz
+ - description:
+ Master/Core clock, must to be >= 62.5 MHz for SS
+ operation and >= 30MHz for HS operation
+ - description:
+ Controller aclk_usb3_rksoc_axi_perf clock
I'm pretty sure these last 3 don't belong to the controller itself,
hence why they were in the glue layer node to being with.
+ - description:
+
Re: [PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
Hi Rob, Heiko,
Version 2 without node wrapper.
Is that OK for backwards compatibility?
New SoC rk3568 and rk3566 in the manufacturer tree also seem to use dwc3
usb, so now only a rk3399 node restyle in mainline with conversion to yaml.
On 2/3/21 5:52 PM, Johan Jonker wrote:
> In the past Rockchip dwc3 usb nodes were manually checked.
> With the conversion of snps,dwc3.yaml as common document
> we now can convert rockchip,dwc3.txt to yaml as well.
> Remove node wrapper.
>
> Added properties for rk3399 are:
> power-domains
> resets
> reset-names
>
> Signed-off-by: Johan Jonker
> ---
> .../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ---
> .../devicetree/bindings/usb/rockchip,dwc3.yaml | 103
> +
> 2 files changed, 103 insertions(+), 56 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> deleted file mode 100644
> index 945204932..0
> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
> +++ /dev/null
> @@ -1,56 +0,0 @@
> -Rockchip SuperSpeed DWC3 USB SoC controller
> -
> -Required properties:
> -- compatible:should contain "rockchip,rk3399-dwc3" for rk3399 SoC
> -- clocks:A list of phandle + clock-specifier pairs for the
> - clocks listed in clock-names
> -- clock-names: Should contain the following:
> - "ref_clk" Controller reference clk, have to be 24 MHz
> - "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
> - "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
> - operation and >= 30MHz for HS operation
> - "grf_clk" Controller grf clk
> -
> -Required child node:
> -A child node must exist to represent the core DWC3 IP block. The name of
> -the node is not important. The content of the node is defined in dwc3.txt.
> -
> -Phy documentation is provided in the following places:
> -Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0
> PHY
> -Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
> -
> -Example device nodes:
> -
> - usbdrd3_0: usb@fe80 {
> - compatible = "rockchip,rk3399-dwc3";
> - clocks = < SCLK_USB3OTG0_REF>, < SCLK_USB3OTG0_SUSPEND>,
> - < ACLK_USB3OTG0>, < ACLK_USB3_GRF>;
> - clock-names = "ref_clk", "suspend_clk",
> - "bus_clk", "grf_clk";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - usbdrd_dwc3_0: dwc3@fe80 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0xfe80 0x0 0x10>;
> - interrupts = ;
> - dr_mode = "otg";
> - };
> - };
> -
> - usbdrd3_1: usb@fe90 {
> - compatible = "rockchip,rk3399-dwc3";
> - clocks = < SCLK_USB3OTG1_REF>, < SCLK_USB3OTG1_SUSPEND>,
> - < ACLK_USB3OTG1>, < ACLK_USB3_GRF>;
> - clock-names = "ref_clk", "suspend_clk",
> - "bus_clk", "grf_clk";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - usbdrd_dwc3_1: dwc3@fe90 {
> - compatible = "snps,dwc3";
> - reg = <0x0 0xfe90 0x0 0x10>;
> - interrupts = ;
> - dr_mode = "otg";
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> new file mode 100644
> index 0..fdf9497bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SuperSpeed DWC3 USB SoC controller
> +
> +maintainers:
> + - Heiko Stuebner
> +
> +description:
> + The common content of the node is defined in snps,dwc3.yaml.
> +
> + Phy documentation is provided in the following places.
> +
> + USB2.0 PHY
> + Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
> +
> + Type-C PHY
> + Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
wrong indentation: expected 2 but found 6 (indentation)
yamllint ./Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
This warning doesn't seem to show up with the command below.
make ARCH=arm64 dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> +
> +allOf:
> + - $ref: snps,dwc3.yaml#
No warning is given here with
[PATCH v2 1/7] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
In the past Rockchip dwc3 usb nodes were manually checked.
With the conversion of snps,dwc3.yaml as common document
we now can convert rockchip,dwc3.txt to yaml as well.
Remove node wrapper.
Added properties for rk3399 are:
power-domains
resets
reset-names
Signed-off-by: Johan Jonker
---
.../devicetree/bindings/usb/rockchip,dwc3.txt | 56 ---
.../devicetree/bindings/usb/rockchip,dwc3.yaml | 103 +
2 files changed, 103 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
deleted file mode 100644
index 945204932..0
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks: A list of phandle + clock-specifier pairs for the
- clocks listed in clock-names
-- clock-names: Should contain the following:
- "ref_clk"Controller reference clk, have to be 24 MHz
- "suspend_clk"Controller suspend clk, have to be 24 MHz or 32 KHz
- "bus_clk"Master/Core clock, have to be >= 62.5 MHz for SS
- operation and >= 30MHz for HS operation
- "grf_clk"Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
-Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
-
-Example device nodes:
-
- usbdrd3_0: usb@fe80 {
- compatible = "rockchip,rk3399-dwc3";
- clocks = < SCLK_USB3OTG0_REF>, < SCLK_USB3OTG0_SUSPEND>,
-< ACLK_USB3OTG0>, < ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- usbdrd_dwc3_0: dwc3@fe80 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe80 0x0 0x10>;
- interrupts = ;
- dr_mode = "otg";
- };
- };
-
- usbdrd3_1: usb@fe90 {
- compatible = "rockchip,rk3399-dwc3";
- clocks = < SCLK_USB3OTG1_REF>, < SCLK_USB3OTG1_SUSPEND>,
-< ACLK_USB3OTG1>, < ACLK_USB3_GRF>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- usbdrd_dwc3_1: dwc3@fe90 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfe90 0x0 0x10>;
- interrupts = ;
- dr_mode = "otg";
- };
- };
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
new file mode 100644
index 0..fdf9497bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+ - Heiko Stuebner
+
+description:
+ The common content of the node is defined in snps,dwc3.yaml.
+
+ Phy documentation is provided in the following places.
+
+ USB2.0 PHY
+ Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+
+ Type-C PHY
+ Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+
+allOf:
+ - $ref: snps,dwc3.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ - rockchip,rk3399-dwc3
+ - const: snps,dwc3
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description:
+ Controller reference clock, must to be 24 MHz
+ - description:
+ Controller suspend clock, must to be 24 MHz or 32 KHz
+ - description:
+ Master/Core clock, must to be >= 62.5 MHz for SS
+ operation and >= 30MHz for HS operation
+ - description:
+ Controller aclk_usb3_rksoc_axi_perf clock
+ - description:
+ Controller aclk_usb3 clock
+ - description:
+ Controller grf clock
+
+ clock-names:
+items:
+ - const: ref_clk
+ - const: suspend_clk
+
