Re: [PATCH v2 14/22] pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
On Sat, Sep 8, 2018 at 4:07 AM wrote: > From: Sean Wang > > Certain SoC own multiple register base for accessing each pin groups, > it's easy to be done with extend struct mtk_pin_field_calc to support > the kind of SoC such as MT8183. > > Signed-off-by: Sean Wang Patch applied. Yours, Linus Walleij
Re: [PATCH v2 14/22] pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
On Sat, Sep 8, 2018 at 4:07 AM wrote: > From: Sean Wang > > Certain SoC own multiple register base for accessing each pin groups, > it's easy to be done with extend struct mtk_pin_field_calc to support > the kind of SoC such as MT8183. > > Signed-off-by: Sean Wang Patch applied. Yours, Linus Walleij
[PATCH v2 14/22] pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
From: Sean Wang
Certain SoC own multiple register base for accessing each pin groups,
it's easy to be done with extend struct mtk_pin_field_calc to support
the kind of SoC such as MT8183.
Signed-off-by: Sean Wang
---
drivers/pinctrl/mediatek/pinctrl-moore.c | 30 +++-
drivers/pinctrl/mediatek/pinctrl-mt7622.c| 2 ++
drivers/pinctrl/mediatek/pinctrl-mt7623.c| 16 ++-
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 36 +++-
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 24
5 files changed, 75 insertions(+), 33 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c
b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 2f3e3b5..2817e47 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -713,25 +713,41 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
{
struct resource *res;
struct mtk_pinctrl *hw;
- int err;
+ int err, i;
hw = devm_kzalloc(>dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
hw->soc = soc;
+ hw->dev = >dev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(>dev, "missing IO resource\n");
- return -ENXIO;
+ if (!hw->soc->nbase_names) {
+ dev_err(>dev,
+ "SoC should be assigned at least one register base\n");
+ return -EINVAL;
}
- hw->dev = >dev;
- hw->base = devm_ioremap_resource(>dev, res);
+ hw->base = devm_kmalloc_array(>dev, hw->soc->nbase_names,
+ sizeof(*hw->base), GFP_KERNEL);
if (IS_ERR(hw->base))
return PTR_ERR(hw->base);
+ for (i = 0; i < hw->soc->nbase_names; i++) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ hw->soc->base_names[i]);
+ if (!res) {
+ dev_err(>dev, "missing IO resource\n");
+ return -ENXIO;
+ }
+
+ hw->base[i] = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(hw->base[i]))
+ return PTR_ERR(hw->base[i]);
+ }
+
+ hw->nbase = hw->soc->nbase_names;
+
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)hw->soc->pins;
mtk_desc.npins = hw->soc->npins;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index 9ac36ab..769b36a 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -768,6 +768,8 @@ static const struct mtk_pin_soc mt7622_data = {
.gpio_m = 1,
.eint_m = 1,
.ies_present = false,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
.bias_disable_get = mtk_pinconf_bias_disable_get,
.bias_set = mtk_pinconf_bias_set,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index 30d2289..1f2030c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -18,15 +18,15 @@
#define BOND_MSDC0E_CLR0x1
#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 15, false)
#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 16, 0)
-#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 16, 1)
#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
@@ -1383,6 +1383,8 @@ static struct mtk_pin_soc mt7623_data = {
.gpio_m = 0,
.eint_m = 0,
.ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
@@ -1402,9 +1404,9 @@ static void mt7623_bonding_disable(struct platform_device
*pdev)
[PATCH v2 14/22] pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
From: Sean Wang
Certain SoC own multiple register base for accessing each pin groups,
it's easy to be done with extend struct mtk_pin_field_calc to support
the kind of SoC such as MT8183.
Signed-off-by: Sean Wang
---
drivers/pinctrl/mediatek/pinctrl-moore.c | 30 +++-
drivers/pinctrl/mediatek/pinctrl-mt7622.c| 2 ++
drivers/pinctrl/mediatek/pinctrl-mt7623.c| 16 ++-
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 36 +++-
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 24
5 files changed, 75 insertions(+), 33 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c
b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 2f3e3b5..2817e47 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -713,25 +713,41 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
{
struct resource *res;
struct mtk_pinctrl *hw;
- int err;
+ int err, i;
hw = devm_kzalloc(>dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
hw->soc = soc;
+ hw->dev = >dev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(>dev, "missing IO resource\n");
- return -ENXIO;
+ if (!hw->soc->nbase_names) {
+ dev_err(>dev,
+ "SoC should be assigned at least one register base\n");
+ return -EINVAL;
}
- hw->dev = >dev;
- hw->base = devm_ioremap_resource(>dev, res);
+ hw->base = devm_kmalloc_array(>dev, hw->soc->nbase_names,
+ sizeof(*hw->base), GFP_KERNEL);
if (IS_ERR(hw->base))
return PTR_ERR(hw->base);
+ for (i = 0; i < hw->soc->nbase_names; i++) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ hw->soc->base_names[i]);
+ if (!res) {
+ dev_err(>dev, "missing IO resource\n");
+ return -ENXIO;
+ }
+
+ hw->base[i] = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(hw->base[i]))
+ return PTR_ERR(hw->base[i]);
+ }
+
+ hw->nbase = hw->soc->nbase_names;
+
/* Setup pins descriptions per SoC types */
mtk_desc.pins = (const struct pinctrl_pin_desc *)hw->soc->pins;
mtk_desc.npins = hw->soc->npins;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index 9ac36ab..769b36a 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -768,6 +768,8 @@ static const struct mtk_pin_soc mt7622_data = {
.gpio_m = 1,
.eint_m = 1,
.ies_present = false,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set,
.bias_disable_get = mtk_pinconf_bias_disable_get,
.bias_set = mtk_pinconf_bias_set,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index 30d2289..1f2030c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -18,15 +18,15 @@
#define BOND_MSDC0E_CLR0x1
#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 15, false)
#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 16, 0)
-#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
- PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit,\
_x_bits, 16, 1)
#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
@@ -1383,6 +1383,8 @@ static struct mtk_pin_soc mt7623_data = {
.gpio_m = 0,
.eint_m = 0,
.ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
.bias_set = mtk_pinconf_bias_set_rev1,
@@ -1402,9 +1404,9 @@ static void mt7623_bonding_disable(struct platform_device
*pdev)
