Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

[Joel Stanley]

On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery  wrote:
>
> RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> single gate for each MAC.
>
> Signed-off-by: Andrew Jeffery 

Reviewed-by: Joel Stanley 

[PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

[Andrew Jeffery]

RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery 
---
v2: Drop "-gate" from clock names

 drivers/clk/clk-aspeed.c | 27 ++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index abf06fb6453e..411ff5fb2c07 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,7 @@
 
 #include "clk-aspeed.h"
 
-#define ASPEED_NUM_CLKS36
+#define ASPEED_NUM_CLKS38
 
 #define ASPEED_RESET2_OFFSET   32
 
@@ -28,6 +28,7 @@
 #define  AST2400_HPLL_BYPASS_ENBIT(17)
 #define ASPEED_MISC_CTRL   0x2c
 #define  UART_DIV13_EN BIT(12)
+#define ASPEED_MAC_CLK_DLY 0x48
 #define ASPEED_STRAP   0x70
 #define  CLKIN_25MHZ_ENBIT(23)
 #define  AST2400_CLK_SOURCE_SELBIT(18)
@@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
 
+   if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
+   /* RMII 50MHz RCLK */
+   hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
+   5000);
+   if (IS_ERR(hw))
+   return PTR_ERR(hw);
+
+   /* RMII1 50MHz (RCLK) output enable */
+   hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+   scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
+   &aspeed_clk_lock);
+   if (IS_ERR(hw))
+   return PTR_ERR(hw);
+   aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
+
+   /* RMII2 50MHz (RCLK) output enable */
+   hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+   scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
+   &aspeed_clk_lock);
+   if (IS_ERR(hw))
+   return PTR_ERR(hw);
+   aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
+   }
+
/* LPC Host (LHCLK) clock divider */
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
-- 
2.20.1