Re: [PATCH v2 2/2] clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks

[Sylwester Nawrocki]

On 11.08.2020 17:12, Sylwester Nawrocki wrote:
> This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related
> clk pointer gets cached in the driver's private data and can be used
> later instead of a __clk_lookup() call.
> 
> With that we have all clocks used in the clk_prepare_enable() calls in the
> clk provider init callback cached in clk_data.hws[] and we can reference
> the clk pointers directly rather than using __clk_lookup() with global names.
> 
> Signed-off-by: Sylwester Nawrocki 
> ---
> Changes for v2:
>  - added missing part of the patch lost during rebase of the previous version

Actually that conflict resolution was incorrect and I squashed 
below patch as a correction.

-8<
>From 1594bdb8fd1ab85e994d638256d214adff4e9d40 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki 
Date: Thu, 17 Sep 2020 11:42:14 +0200
Subject: [PATCH] clk: samsung: exynos5420: Fix assignment of hws

Fix incorrect rebase conflict resolution.

Reported-by: Marek Szyprowski 
Signed-off-by: Sylwester Nawrocki 
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c 
b/drivers/clk/samsung/clk-exynos5420.c
index ba4e0a4..3ccd4ea 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1574,6 +1574,7 @@ static void __init exynos5x_clk_init(struct device_node 
*np,
exynos5x_soc = soc;
 
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
+   hws = ctx->clk_data.hws;
 
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
@@ -1651,7 +1652,6 @@ static void __init exynos5x_clk_init(struct device_node 
*np,
 exynos5x_subcmus);
}
 
-   hws = ctx->clk_data.hws;
/*
 * Keep top part of G3D clock path enabled permanently to ensure
 * that the internal busses get their clock regardless of the
-- 
2.7.4
-8<

[PATCH v2 2/2] clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks

[Sylwester Nawrocki]

This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related
clk pointer gets cached in the driver's private data and can be used
later instead of a __clk_lookup() call.

With that we have all clocks used in the clk_prepare_enable() calls in the
clk provider init callback cached in clk_data.hws[] and we can reference
the clk pointers directly rather than using __clk_lookup() with global names.

Signed-off-by: Sylwester Nawrocki 
---
Changes for v2:
 - added missing part of the patch lost during rebase of the previous version
---
 drivers/clk/samsung/clk-exynos5420.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c 
b/drivers/clk/samsung/clk-exynos5420.c
index bd62087..f76ebd6 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -712,8 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] 
__initconst = {
SRC_TOP12, 8, 1),
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
SRC_TOP12, 12, 1),
-   MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
- CLK_SET_RATE_PARENT, 0),
+   MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
+   SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
SRC_TOP12, 20, 1),
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
@@ -1560,6 +1560,7 @@ static void __init exynos5x_clk_init(struct device_node 
*np,
enum exynos5x_soc soc)
 {
struct samsung_clk_provider *ctx;
+   struct clk_hw **hws;
 
if (np) {
reg_base = of_iomap(np, 0);
@@ -1649,17 +1650,18 @@ static void __init exynos5x_clk_init(struct device_node 
*np,
 exynos5x_subcmus);
}
 
+   hws = ctx->clk_data.hws;
/*
 * Keep top part of G3D clock path enabled permanently to ensure
 * that the internal busses get their clock regardless of the
 * main G3D clock enablement status.
 */
-   clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
+   clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
/*
 * Keep top BPLL mux enabled permanently to ensure that DRAM operates
 * properly.
 */
-   clk_prepare_enable(__clk_lookup("mout_bpll"));
+   clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
 
samsung_clk_of_add_provider(np, ctx);
 }
-- 
2.7.4